SLVK282 April 2026 ISOS510-SEP
The primary concern for the ISOS510-SEP is the robustness against single-event latch-up (SEL). In mixed technologies such as the BiCMOS process used on the ISOS510-SEP , the CMOS circuitry introduces a potential for SEL susceptibility.
SEL can occur if excess current injection caused by the passage of an energetic ion is high enough to trigger the formation of a parasitic cross-coupled PNP and NPN bipolar structure (formed between the p-sub and n-well and n+ and p+ contacts) [1,2]. The parasitic bipolar structure initiated by a single-event creates a high-conductance path (inducing a steady-state current that is typically orders-of-magnitude higher than the normal operating current) between power and ground that persists (is “latched”) until power is removed, the device is reset, or until the device is destroyed by the high-current state. The ISOS510-SEP was tested for SEL at the maximum recommended operating conditions of input forward current (IF) of 10mA and collector-emitter voltage (VCE) of 30V. During testing of the three devices, the ISOS510-SEP did not exhibit any SEL with heavy-ions with LETEFF = 47MeV×cm2/mg at flux of approximately 105ions×cm2/s , fluence of approximately 1 × 107 – 1.5 × 107ions/cm2, and a die temperature of 125°C.
The ISOS510-SEP was characterized for SET at flux of 105ions×cm2/s , fluences of 1 × 107 – 1.5 × 107ions/cm2, and room temperature conditions. The device was characterized at IF of approximately 1.9mA and VCE of 3.3V. Heavy-ions with LETEFF from 1.34 to 47MeV×cm2/mg were used to characterize the transient performance. To see the SET results of the ISOS510-SEP, please refer to Single-Event Transients (SET) Results.