SLVAFF0 September   2022 TPS25947 , TPS2597 , TPS25981 , TPS25982 , TPS25985

 

  1.   Abstract
  2.   Trademarks
  3. 1Understanding the FET SOA
  4. 2Ensuring FET SOA in Hot-Swap Design
  5. 3eFuse Ensuring Integrated FET SOA Operation
    1. 3.1 Thermal Shutdown
    2. 3.2 eFuse Response to Events Stressing Integrated FET
  6. 4Plotting eFuse AOA
  7. 5eFuse Application Design Recommendations to Ensure Integrated FET Reliability
  8. 6Summary
  9. 7References

Thermal Shutdown

Discrete protection realizations need careful selection of pass FET and thermal design to keep the device in SOA limits under all fault conditions. However, TI eFuses come with inbuilt over temperature protection and shuts down if the eFuse junction temperature, TJ , exceeds 154°C (typ). A thermal shutdown circuit typically detects that a power IC is overheating, by measuring the absolute junction temperature of the hottest areas on the chip. Thermal monitors are usually positioned in the power transistor area where most of the power dissipates. A thermal monitoring circuit translates the junction temperature to a voltage or current level that is then compared to a reference level (the absolute threshold, or TABS) corresponding to a temperature below the safe limit for the IC. If the junction temperature is above TABS, then the eFuse shuts down. For more detail on thermal shutdown scheme, please refer to chapter 7 of this 11 Ways to Protect Your Power Path white paper.

Figure 3-1 Thermal Shutdown Scheme