SLVAFF0 September   2022 TPS25947 , TPS2597 , TPS25981 , TPS25982 , TPS25985

 

  1.   Abstract
  2.   Trademarks
  3. 1Understanding the FET SOA
  4. 2Ensuring FET SOA in Hot-Swap Design
  5. 3eFuse Ensuring Integrated FET SOA Operation
    1. 3.1 Thermal Shutdown
    2. 3.2 eFuse Response to Events Stressing Integrated FET
  6. 4Plotting eFuse AOA
  7. 5eFuse Application Design Recommendations to Ensure Integrated FET Reliability
  8. 6Summary
  9. 7References

3 eFuse Ensuring Integrated FET SOA Operation

To achieve robust, high power density and lower cost power path protection design, system designers are using eFuse. eFuse provides the same functionality as hot-swap controllers but it also integrates power FET, and thus eliminates lot of complexities compared to the designs using external FETs. eFuse is designed using protection schemes like thermal shutdown, current limit, fast-trip that ensures integrated FET SOA operation under stress conditions. In external FET design, integrated thermal shutdown feature is not available because of which system designer needs to manage FET SOA.

SOA of an eFuse can be interpreted similar to external FET SOA. eFuse SOA can be divided into regions and region boundary is decided by parameters like RDS(ON) and protection schemes of eFuse. The following show which protection scheme takes care of which region of SOA.

  • Electrical SOA – It is the region of SOA which is limited by maximum current supported for different pulse durations. Current limit and short circuit protection features ensure that eFuse does not operate beyond this boundary.
  • Thermal SOA – This region is the same as power limit region of FET SOA. eFuse thermal shutdown protection feature decides boundary of this region.eFuse supports certain pulse power before thermal shutdown would turn it off.
  • Electro-thermal SOA – Industry is shifting towards high-power density designs that offer high current with very low RDS(ON) and area. FETs offering such specifications have reduced available SOA at higher VDS known as spirito effect. Mismatch in current among multiple parallel cells increases power dissipation in those cells which further increases mismatch in current and forms a positive feedback loop between electrical and thermal parameter resulting in formation of hot-spots on FET die. Thermal instability region of FET SOA depicts this effect.

Our high power density eFuses such as TPS25947, TPS2597, TPS25981, and TPS25985 have a proprietary protection mechanism. This mechanism anticipates that integrated FET may go into thermal runaway condition and turn off the FET early thus ensuring the FET operation in SOA. When eFuse turns-on under output short circuit condition, the integrated FET experiences the most VDS stress and the chances of thermal runaway are the highest. Therefore, Texas Instrument eFuses are subjected to such tests repetitively during the qualification process. This qualification process ensures robustness of TI eFuse and proves the working of the integrated protection mechanisms.

SOA of eFuse can be termed as AOA (allowed operating area) as the safe region of operation is decided by protection schemes and eFuse is not allowed to operate beyond that AOA.