SLVAFF0 September   2022 TPS25947 , TPS2597 , TPS25981 , TPS25982 , TPS25985

 

  1.   Abstract
  2.   Trademarks
  3. 1Understanding the FET SOA
  4. 2Ensuring FET SOA in Hot-Swap Design
  5. 3eFuse Ensuring Integrated FET SOA Operation
    1. 3.1 Thermal Shutdown
    2. 3.2 eFuse Response to Events Stressing Integrated FET
  6. 4Plotting eFuse AOA
  7. 5eFuse Application Design Recommendations to Ensure Integrated FET Reliability
  8. 6Summary
  9. 7References

4 Plotting eFuse AOA

Graphical representation of eFuse Allowed Operating Area (AOA) similarly like FET SOA can be obtained as discussed below. For example of TPS2597 eFuse and see how the boundary imposed by these protection schemes, eFuse RDS(ON) and maximum recommended VIN rating can be plotted on a log-log graph at 25°C ambient temperature.

  1. RDS(ON) limited region is a line with slope equal to maximum RON of TPS2597 at 25°C which is 18.3 mΩ.
  2. BVDSS limited region is a line parallel to Y axis that intersects X-axis at maximum recommended VIN of 23 V.
  3. Current limit region for DC power is a line parallel to X-axis with height equal to maximum dc continuous current spec of eFuse which is 7 A. In TPS2597 because of ITIMER feature we can allow current greater than 7.7A and less than 2×7.7=15.4 A for ITIMER duration. For power pulses of duration less than equal to 10 ms a zero slope line of height 14 A represents current limit line. 14A is double the minimum current limit value of 7 A (value in the electrical characteristics table of the data sheet) for 8 A current limit setting.
  4. Power limit region:
    1. To plot this region for lower VDS range, steady state time to thermal shutdown vs. power dissipation plot at 25°C in the data sheet can be used. This plot tells that for a certain power how much time will it take for eFuse to thermal shutdown. This curve can also be interpreted as for a pulse of certain time duration how much maximum power can be supported before eFuse hits thermal shutdown. Also this data is provided at different ambient temperatures, so to plot AOA at different temperature this data can be used directly unlike in external FET design where derating has to be done on FET SOA at 25°C to obtain SOA at other temperatures.
    2. Suppose power limit for 10 ms pulse is to be plotted. Power value that causes TSD in 10 ms can be obtained from TSD curve. Then a line can be plotted on AOA curve such that product of VDS and IDS is equal to that power value.
    3. Similar procedure can be repeated for pulses of other duration.
    4. For higher VDS range inrush Time to TSD vs PD curve present in data sheet needs to be used. Boundary of AOA obtained from this curve is imposed by proprietary protection mechanism that is not letting integrated FET to thermal runaway.

Figure 4-1 plot is obtained for TPS2597.

Figure 4-1 TPS2597 AOA