SLVAF55 July   2021 TPS62130 , TPS62901 , TPS62902 , TPS62903

 

  1.   Trademarks
  2. 1Introduction
  3. 2Power Density
  4. 3Achieving a Smaller Solution
    1. 3.1 Smaller Package and Fewer External Components
    2. 3.2 Smart Configuration Pin
    3. 3.3 VSET
  5. 4Reducing Power Loss
    1. 4.1 Junction Temperature
    2. 4.2 Automatic Efficiency Enhancement (AEE™)
    3. 4.3 1MHz and 2.5MHz Switching Frequencies
    4. 4.4 Auto PFM/PWM vs. Forced PWM
  6. 5Application Flexibility
    1. 5.1 Quiescent Current
    2. 5.2 Lower and More Accurate Output Voltages
    3. 5.3 Capacitive Discharge
  7. 6Summary
  8. 7References

3.1 Smaller Package and Fewer External Components

The QFN package of TPS6290x is one third the size of the previous generation, however the size of the package is not the only thing that has shrunk. The total solution size is reduced by more than 30% as well. To achieve both of these reductions, TPS6290x has decreased the number of pins on the package from 16 to 9, allowing the package to shrink and decreasing the passives needed to configure the device. The result saves precious board space, BOM costs and design time.

GUID-EE3C1399-138A-497D-9FCF-8F54C08D2755-low.gif Figure 3-1 Typical application schematic of the TPS621x0
GUID-20201109-CA0I-J5GD-T3WX-VZKLDHRX75BQ-low.gif Figure 3-2 Typical application schematic of the TPS6290x