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  • Thermal Comparison of a DC-DC Converter in SOT23 and the New SOT563

    • SLVAEB1A March   2020  – October 2021 TLV62568 , TLV62569 , TLV62585

       

  • CONTENTS
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  • Thermal Comparison of a DC-DC Converter in SOT23 and the New SOT563
  1.   Trademarks
  2. 1Introduction
  3. 2Describing the TLV62569 Package Technologies: SOT23-5, SOT23-6, and SOT563
  4. 3Understanding Thermal Performance and Junction Temperature Estimation
    1. 3.1 Understanding Thermal Performance
    2. 3.2 Estimating Junction Temperature
  5. 4Measurement Setup and Test Results
    1. 4.1 Efficiency Measurements
    2. 4.2 Thermal Measurements
  6. 5Thermal Performance Analysis for SOT23-5, SOT23-6, and SOT563 Packages
    1. 5.1 Comparing SOT563 (DRL) and SOT23-6 (DDC)
    2. 5.2 Comparing SOT23-6 (DDC) and SOT23-5 (DBV)
    3. 5.3 Comparing SOT563 (DRL) and SOT23-5 (DBV)
  7. 6Summary
  8. 7References
  9. 8Revision History
  10. IMPORTANT NOTICE
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APPLICATION NOTE

Thermal Comparison of a DC-DC Converter in SOT23 and the New SOT563

Trademarks

WEBENCH is a registered trademark of Texas Instruments.

All trademarks are the property of their respective owners.

1 Introduction

There is a strong trend towards smaller form factors in electronic board designs. At the same time, there is also an increasing need for more power rails and, in some cases, higher currents to supply digital cores like Micro-Controller Units (MCU), field-programmable Gate Arrays (FPGA), or other embedded processors. In terms of power design, this translates into the need for integrated circuits (ICs) with higher power density where thermal design becomes critical to achieve the required performance without compromising cost. This application report focuses on DC/DC converters in SOT23 and the new, 65% smaller, SOT563 packages. More specifically on the performance differences of a same non-isolated 5-V/2-A buck converter (TLV62569) in three different packages: SOT 23-5, SOT23-6, and SOT563.

After an overview of the SOT23 and SOT563 packaging technology, this application report shows the thermal performances of the TLV62569 in different packages and discusses the impact in specific power designs. It also introduces the performance differences of 17 V/3 A series parts between SOT236 and SOT563 package. TPS56x201/8 is 17 V 1~5 A series part with SOT236 package. TPS56x202/7 is 17V 2~3 A series part with SOT563 package. Table 1-1 shows the part number of these two family parts. Finally, it summarizes the advantages of each package to help the designer choose the right package for addressing key challenges in his/her end equipment.

Table 1-1 Some 17V Part Number of SOT236 and SOT563 Package
Description SOT236 SOT563
17 V/1 A TPS561201/8
17 V/2 A TPS562201/8

TPS562202/7

TPS562202/7S

17 V/3 A TPS563201/8

TPS563202/7

TPS563202/7S

17 V/4 A TPS564201/8
17 V/5 A TPS565201/8

2 Describing the TLV62569 Package Technologies: SOT23-5, SOT23-6, and SOT563

The TLV62569 device is a synchronous step-down converter optimized for high efficiency and compact solution size. The device integrates switches capable of delivering an output current up to 2 A. As shown in Table 2-1, this device is available in three different packages: SOT23-5, SOT23-6, and SOT563. In the three packages, the die area remains the same for this device.

Table 2-1 Device Information
PART NUMBER PACKAGE BODY SIZE (NOM)
TLV62569DBV SOT23 (5) 2.90-mm × 2.80-mm
TLV62569PDDC SOT23 (6)
TLV62569DRL SOT563 (6) 1.60-mm × 1.60-mm
TLV62569PDRL SOT563 (6)

As of today, SOT23 packages are widely used in several applications because of their ease of use.

Even though the SOT23-5 (DBV) and SOT23-6 (DDC) share the same package appearance with the same footprint dimensions, these two packages use different interconnection between silicon and package itself. The SOT23-5 (DBV) is designed with a bonding wire interconnection structure whereas the SOT23-6 uses the Flip Chip On Lead (FCOL) approach. Connecting the IC with wire bonds using copper, gold, or aluminum wires inside the package has the advantage of being flexible and cost effective. However, it requires space and the bonding wires add parasitic inductance and resistance on the pins. On the contrary, with the FCOL package technology, copper bumps are used as interconnection and they are directly located on the die. Therefore there is no additional parasitic inductance and resistance added due to the interconnection structure. For more details on SOT23-5 and SOT23-6 packages, see the SOT23 Package Thermal Consideration Application Report.

Similar to the SOT23-6, the new SOT563 (DRL) package is also based on FCOL bonding structure. But SOT563 package interconnection is also different with SOT236 package. Figure 2-1 shows SOT563(DRL) package assembly technology. For SOT236 package, die is under leadframe. As for SOT563 package, die is on leadframe. Obviously lead of SOT563 is shorter. Short lead will lead to small parasitic resister and inductance. Thanks to innovations in packaging structures and lead frame designs, it is possible to achieve a 65% smaller IC package compared to SOT23-5 and SOT23-6 for the same die area without compromising thermal performance. Table 3-3 shows that the junction to top and junction to board thermal characteristics ψJT and ψJB are the smallest for the DRL package, translating directly in a better heat dissipation of the junction to top and junction to board. Table 3-4 shows TPS563201 and TPS563202 part thermal metric. ψJT of TPS563202 is smaller than TPS563201 which also shows DRL package has a better heat dissipation of the junciton to top.

Figure 2-1 SOT563 package

3 Understanding Thermal Performance and Junction Temperature Estimation

3.1 Understanding Thermal Performance

Having good thermal performances could have various meanings depending on the end equipment (EE).

Some systems, like Industrial PCs, have a specified board temperature you cannot exceed. In this case, the board designer has to ensure that the heat dissipation of the IC is optimized through a good layout and cooling system. In other end equipment, like security cameras, a defined operating ambient temperature is required and the designer needs to ensure that the IC stays within the specified recommended operating junction temperature for reliable operation. In other systems, like Solid State Drive (SSD) Memories, the board heats up mainly from other ICs, like the SSD controller. In such cases, the heat dissipation through the board is limited due to its restricted size and form factor. The system designer needs to make sure the power IC package is able to support a good board to top heat dissipation to stay within the recommended junction temperature and avoid unwanted behavior like thermal shutdown.

3.2 Estimating Junction Temperature

The junction temperature of the IC is a crucial parameter for good thermal design. For further details on thermal parameters of ICs, see the Semiconductor and IC Package Thermal Metrics Application Report.

The reliable method to estimate the junction temperature of a DC/DC converter is to use the junction-to-board characterization parameter of the IC, ψJT , specified in Table 3-2 of the TLV62569 2-A High Efficiency Synchronous Buck Converter in SOT Package Data Sheet with Equation 1.

Equation 1. Tj = ψJT × PIC, diss + Tcase
Table 3-1 Variables Description for Junction Temperature Calculation
PARAMETER DESCRIPTION COMMENTS
Tj IC junction temperature Target value to calculate
Tcase IC case temperature Can be easily measured for given operating condition with a thermal camera as shown on figure 1.
ψJT Junction-to-top characterization parameter Specified in the TLV62569 2-A High Efficiency Synchronous Buck Converter in SOT Package Data Sheet. See table 1.
PIC, diss Dissipated power in the IC for the given operating conditions This parameter needs to be estimated carefully to have more reliable results (see below).

There are two options to estimate the IC power dissipation PIC,diss. The first and easiest option to estimate PIC,diss is the WEBENCH® Power Designer Tool for the required operating conditions. The second option is to use Equation 2:

Equation 2. PIC,diss = Pdiss – Pind
Table 3-2 Variables Description for IC Power Dissipation Calculation
PARAMETER DESCRIPTION COMMENTS
PIC, diss IC power dissipation
Pdiss Total dissipated power
Pdiss = (1 - n) × (Pout / η )
Pout: Output power
η : Efficiency of the power stage – can be found in the TLV62569 2-A High Efficiency Synchronous Buck Converter in SOT Package Data Sheet or modeled in WEBENCH®
Pind DC power losses in inductor
Pind = DCR × Iout2
DCR: inductor series resistor
This parameter can be simulated in some manufacturer's website or in WEBENCH®

It is important to model the dissipated power in the inductor to have a more reliable estimation of the junction temperature. As a general rule, it is good enough to model only the DC losses of the inductor.

Table 3-3 IC Thermal Information
THERMAL METRICDEV (5 PINS)DDC (6 PINS)DRL (6 PINS)UNIT
RθJA188.2106.2146.3°C/W
RθJC(top)137.552.951.0°C/W
RθJB41.231.227.0°C/W
ψJT31.411.32.2°C/W
ψJB40.631.627.6°C/W
RθJC(bot)N/AN/AN/A°C/W
Table 3-4 Thermal Metric of TPS563201 and TPS563202 Package
THERMAL METRIC TPS563201 TPS563202 UNIT
RθJA 92.6 137 °C/W
RθJA_Effective 53.0 65.0 °C/W
RθJC(top) 48.5 43.2 °C/W
RθJB 15.5 22.0 °C/W
ψJT 2.5 0.9 °C/W
ψJB 15.5 21.8 °C/W

In this section, the different relevance of thermal performance across EE applications were explained and the important parameters for good thermal performance evaluation were introduced. The next section focuses on the specific thermal performance of the TLV62569 across the three different packages: SOT23-5, SOT23-6, and SOT563. And introduces TPS563201 and TPS563202 performance.

4 Measurement Setup and Test Results

This section shows a comparison of the performances of the TLV62569 which has the same die area in the three packages: SOT23-5 (DBV), SOT23-6 (DDC), and SOT563 (DRL).

For analyzing the thermal performance across the three different packages, the efficiency is measured on the three different Evaluation Modules (EVM) shown in Table 4-1. The case temperature is measured with a thermal camera as shown in Figure 4-1 and the junction temperature is estimated using Equation 1 as explained in the previous section.

GUID-1243E0A8-AC05-42EE-8BC8-4615C8B04292-low.gifFigure 4-1 Case Temperature Measurement with a Thermal Camera
Table 4-1 EVMs Used for Measurements
SOT23-5 PACKAGE (DBV)
TLV62569EVM-789
SOT23-6 PACKAGE (DDC)
TLV62569EVM-884
SOT563 PACKAGE (DRL)
TLV62569EVM-860
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