There is a strong trend towards smaller form factors in electronic board designs. At the same time, there is also an increasing need for more power rails and, in some cases, higher currents to supply digital cores like Micro-Controller Units (MCU), field-programmable Gate Arrays (FPGA), or other embedded processors. In terms of power design, this translates into the need for integrated circuits (ICs) with higher power density where thermal design becomes critical to achieve the required performance without compromising cost. This application report focuses on DC/DC converters in SOT23 and the new, 65% smaller, SOT563 packages. More specifically on the performance differences of a same non-isolated 5-V/2-A buck converter (TLV62569) in three different packages: SOT 23-5, SOT23-6, and SOT563.

After an overview of the SOT23 and SOT563 packaging technology, this application report shows the thermal performances of the TLV62569 in different packages and discusses the impact in specific power designs. It also introduces the performance differences of 17 V/3 A series parts between SOT236 and SOT563 package. TPS56x201/8 is 17 V 1~5 A series part with SOT236 package. TPS56x202/7 is 17V 2~3 A series part with SOT563 package. Table 1-1 shows the part number of these two family parts. Finally, it summarizes the advantages of each package to help the designer choose the right package for addressing key challenges in his/her end equipment.

The TLV62569 device is a synchronous step-down converter optimized for high efficiency and compact solution size. The device integrates switches capable of delivering an output current up to 2 A. As shown in Table 2-1, this device is available in three different packages: SOT23-5, SOT23-6, and SOT563. In the three packages, the die area remains the same for this device.

As of today, SOT23 packages are widely used in several applications because of their ease of use.

Even though the SOT23-5 (DBV) and SOT23-6 (DDC) share the same package appearance with the same footprint dimensions, these two packages use different interconnection between silicon and package itself. The SOT23-5 (DBV) is designed with a bonding wire interconnection structure whereas the SOT23-6 uses the Flip Chip On Lead (FCOL) approach. Connecting the IC with wire bonds using copper, gold, or aluminum wires inside the package has the advantage of being flexible and cost effective. However, it requires space and the bonding wires add parasitic inductance and resistance on the pins. On the contrary, with the FCOL package technology, copper bumps are used as interconnection and they are directly located on the die. Therefore there is no additional parasitic inductance and resistance added due to the interconnection structure. For more details on SOT23-5 and SOT23-6 packages, see the SOT23 Package Thermal Consideration Application Report.

Similar to the SOT23-6, the new SOT563 (DRL) package is also based on FCOL bonding structure. But SOT563 package interconnection is also different with SOT236 package. Figure 2-1 shows SOT563(DRL) package assembly technology. For SOT236 package, die is under leadframe. As for SOT563 package, die is on leadframe. Obviously lead of SOT563 is shorter. Short lead will lead to small parasitic resister and inductance. Thanks to innovations in packaging structures and lead frame designs, it is possible to achieve a 65% smaller IC package compared to SOT23-5 and SOT23-6 for the same die area without compromising thermal performance. Table 3-3 shows that the junction to top and junction to board thermal characteristics ψ_JT and ψ_JB are the smallest for the DRL package, translating directly in a better heat dissipation of the junction to top and junction to board. Table 3-4 shows TPS563201 and TPS563202 part thermal metric. ψ_JT of TPS563202 is smaller than TPS563201 which also shows DRL package has a better heat dissipation of the junciton to top.

Having good thermal performances could have various meanings depending on the end equipment (EE).

Some systems, like Industrial PCs, have a specified board temperature you cannot exceed. In this case, the board designer has to ensure that the heat dissipation of the IC is optimized through a good layout and cooling system. In other end equipment, like security cameras, a defined operating ambient temperature is required and the designer needs to ensure that the IC stays within the specified recommended operating junction temperature for reliable operation. In other systems, like Solid State Drive (SSD) Memories, the board heats up mainly from other ICs, like the SSD controller. In such cases, the heat dissipation through the board is limited due to its restricted size and form factor. The system designer needs to make sure the power IC package is able to support a good board to top heat dissipation to stay within the recommended junction temperature and avoid unwanted behavior like thermal shutdown.

The junction temperature of the IC is a crucial parameter for good thermal design. For further details on thermal parameters of ICs, see the Semiconductor and IC Package Thermal Metrics Application Report.

The reliable method to estimate the junction temperature of a DC/DC converter is to use the junction-to-board characterization parameter of the IC, ψ_JT , specified in Table 3-2 of the TLV62569 2-A High Efficiency Synchronous Buck Converter in SOT Package Data Sheet with Equation 1.

There are two options to estimate the IC power dissipation P_IC,diss. The first and easiest option to estimate P_IC,diss is the WEBENCH® Power Designer Tool for the required operating conditions. The second option is to use Equation 2:

It is important to model the dissipated power in the inductor to have a more reliable estimation of the junction temperature. As a general rule, it is good enough to model only the DC losses of the inductor.

In this section, the different relevance of thermal performance across EE applications were explained and the important parameters for good thermal performance evaluation were introduced. The next section focuses on the specific thermal performance of the TLV62569 across the three different packages: SOT23-5, SOT23-6, and SOT563. And introduces TPS563201 and TPS563202 performance.

This section shows a comparison of the performances of the TLV62569 which has the same die area in the three packages: SOT23-5 (DBV), SOT23-6 (DDC), and SOT563 (DRL).

For analyzing the thermal performance across the three different packages, the efficiency is measured on the three different Evaluation Modules (EVM) shown in Table 4-1. The case temperature is measured with a thermal camera as shown in Figure 4-1 and the junction temperature is estimated using Equation 1 as explained in the previous section.

Figure 4-1 Case Temperature Measurement with a Thermal Camera

Table 4-1 EVMs Used for Measurements

SOT23-5 PACKAGE (DBV) TLV62569EVM-789	SOT23-6 PACKAGE (DDC) TLV62569EVM-884	SOT563 PACKAGE (DRL) TLV62569EVM-860

For all the EVM boards using the same Bill of Materials (BOM) excluding the TLV62569 ICs, the efficiency is measured for an input voltage of Vin = 5.0 V and an output voltage of Vout = 3.3 V.

Figure 4-2 shows the results and the following two key points can be derived as shown in Table 4-2.

Figure 4-2 Efficiency Measurements on TLV62569 EVMs for Vin = 5 V and Vout = 3.3 V

It also tests TPS563201 and TPS563202 performance. This test is on their public EVM board and test condition is 12Vin to 1Vout with same BOM. Figure 4-3 shows efficiency comparison between TPS563201 and TPS563202. From the figure, efficiency is similar at light loading. At full 3A loading, TPS563201 efficiency is a little higher than TPS563202.

As a first step to evaluate the thermal performances on all three EVM boards, the case temperature of the IC is measured using a thermal camera for Vin = 5 V, Vout = 3.3 V over a load range of 250 mA to 2 A. Table 4-3 show an example of thermal pictures captured for Iout = 2A.

Table 4-3 Thermal Picture on TLV62569 EVMs at Vin = 5 V, Vout = 3.3 V, and Iout = 2 A

SOT23-5 PACKAGE	SOT23-6 PACKAGE	SOT563 PACKAGE (DRL)
Case temperature: Tcase = 65°C	Case temperature: Tcase = 53°C	Case temperature Tcase = 72°C

The results of IC case temperature measurements over the entire load range up to 2 A are compiled in Figure 4-4. As a next step, the junction temperatures of the IC in the three different packages are deducted using Equation 1. Figure 4-5 shows the results.

The thermal measurements are represented versus output current and IC power dissipation to demonstrate the linear relation between IC temperature and IC power dissipation on each of the EVMs.

Figure 4-4 Case Temperature vs. Dissipated Power

Figure 4-5 Case Temperature vs. Output Current

Figure 4-6 Calculated Junction Temperature vs. Dissipated Power

Figure 4-7 Calculated Junction Temperature vs. Output current

Thermal performances are critical for higher load current as power dissipation becomes a challenge with conduction losses increasing.

From graphs on Figure 4-2, Figure 4-4, and Table 4-4, three main observations can be made:

• SOT23-5 has the highest junction temperature.
• SOT23-6 has the lowest Junction and case temperature.
• SOT563 has the lowest junction to top temperature raise.

Figure 4-8 shows thermal comparison of TPS563201 and TPS563202. Because of different theta JA, TPS563201 thermal performance is a little better than TPS563202.

This section concentrated on the method to measure and estimate IC temperature and tangible results were shown for the TLV62569. Moving forward, the focus is set on the analysis of these measurement results and the meaning in terms of IC packaging.