The dead-time between PWMH falling edge and PWML rising edge (tz) serves as the wait time for V_SW transition from its high level down to the target ZVS point. Since the optimal tZ varies with V_BULK, the internal dead-time optimizer automatically extends tz as V_BULK is less than the highest voltage of the input bulk capacitor (V_BULK(MAX)). The circulating energy for ZVS can be further reduced, obtaining higher efficiency at low line versus a fixed dead-time over a wide line voltage range. A resistor on the RTZ pin (R_RTZ) programs the minimum tZ (t_Z(MIN)) at V_BULK(MAX), which is the sum of the propagation delay of the high-side driver (t_D(DR)) and the minimum resonant transition time of V_SW falling edge (t_LC(MIN)).

Normally the RTZ is designed as calculator result. If the VDS voltage has ring back voltage as Figure 4-3 showing, you need to reduce the RTZ resistance.