SLUAAG2 October 2021 UCC28782
TI has several publications and reference design to assist customers with designing the UCC28782. The following are some of the publications to assist with customer design.
Selecting the correct reference design as a starting point
Using calculator to design parameter
After choosing the correct reference design, the user can customize the parameter with their spec by calculator, UCC28782 calculator includes the IC parameter design and transformer design and secondary side resonance tuning and feedback loop design with TL431, so it is very helpful for customer to design the ACF board.
UCC28782 design calculator tool
Refer the layout guidelines with the data sheet section 11
Review the schematic and layout with checklist
The the schematic and layout design is completed, refer to the checklist shown in Table 3-1 and Table 3-2, so the user can double check that they did not miss any significant item.
UCC28782 system bring up guideline and debug FAQ
After the schematic and layout is finished, the user needs to evaluate the board, and might also face several issue. The user can refer to the application note for these item to speed up the debugging.
UCC28782 system timing up guideline and debug FAQ:
EMI filter design
After the system performance meets the spec without issue, the user needs to fine tune the EMI. TI has several application notes to assist with EMI tuning that include the following:
| Checklist item | Purpose |
|---|---|
| The high-side driver with short power-on delay less than 10 μs | Make sure the high side GaN switching can follow PWMH signal immediately |
| Boostrap diode trr around 35ns | boostrap capacitor voltage charged quickly |
| Add 24 V or 27 V TVS at BIN pin | BIN and BSW pin voltage rating is 30V, so add TVS to prevent it damaged |
| Choice the boost inductor with higher than 0.4-A saturation current capability and DCR less than 1 Ω resistance | Prevent it trigger the survival mode easily |
| RVS1 using 0805 package | The voltage at RVS1 would up to 100V for 20V PD application |
| Choice the capacitor with low DC bias influenced at BIN, VDD, and Co1 | The capacitor may use 35V rating, but its capacitance is derating during 20Vo |
| Choice the optocoupler with higher CTR and low temperature variation, TLP383 or FODM8801A is suggested | Prevent the lower low frequency gain to suppress the AC ripple. |
| add the Rdiff and Cdiff at feedback loop | For dynamic load performance tuning |
| Add the bi-direction TVS diode at depletion FET GS pin | Protect the depletion FET |
| Reserve the Rrun and Drun | For LPM to ABM transition tuning |
| Add serial damping inductor with 1206 package | Improve the stability at ABM |
| SR MOS with 150 V rating for ACF 20V PD application,reserve the TVS at SR DS site | SR spike is observed at output voltage transition and SCP and LPM to ABM |
| Reserve the RC filter at high side GaN PWM input pin | Prevent the GaN fault turn on by noise |
| Completed | Layout Checklist |
|---|---|
| Minimize the power stage high dv/dt, di/dt, and dB/dt loop to prevent noise coupling to noise sensitive signals, and get better EMI performance | |
| GaN thermal dissipate by the PCB, make sure add enough via at GaN copper | |
| Avoid any trace overlap with VS pin trace, and minimize the VS pin trace | |
| Minimize these high dv/dt trace Vaux, BSW, and SWS to prevent noise coupling to noise sensitive signals | |
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Make sure these component close to IC to minimize noise coupling: RRDM, RRTZ, RFB, CFB, RVS2, RBUR1, RBUR2, CBUR, Cref, CS pin RC filter, BIN pin TVS, CP13, CBIN2, and CVDD |
|
| Minimize the FB and CS loop to minimize noise coupling | |
| Csws and Dsws ground connect to Cbulk ground | |
| For GaN setting, RVS2 ground connect to SET pin and SET pin connect to thermal pad directly, and minimize the ground connection at set pin. | |
| AGND: the decoupling capacitors for REF, CS, BUR, and P13 connect to AGND, and use kelvin connection to Rsense return path. | |
| BGND: boost ground, CBIN, CVDD, and Auxwinding ground path connect to BGND, and connect to AGND at thermal pad or CVDD ground. | |
| PGND : gate driver return for PWML signal, if using the GaN with integrated gate driver, PGND connect to thermal pad directly, if not, connect to source pin of low side FET. | |
| Provide the shielding with ground planes on these pin : BUR pin and FB loop | |
| Avoide the shielding with ground planes on these pin : RDM, RTZ, and VS pin | |
| Make sure the RC filter for high side GaN PWM input pin close to GaN |