SLLU149E June   2011  – February 2016 TUSB7320 , TUSB7340

 

  1.   TUSB73x0 Board Design and Layout Guidelines
    1.     Trademarks
    2.     Related Documentation
  2. 1 Typical System Implementation
    1. 1.1 Overview
  3. 2 Power
    1. 2.1 Overview
    2. 2.2 Digital Supplies
    3. 2.3 Analog Supplies
    4. 2.4 Ground Terminal
    5. 2.5 Capacitor Selection Recommendations
    6. 2.6 USB VBUS
  4. 3 Device Reset
    1. 3.1 Overview
  5. 4 General High Speed Layout Guidelines
    1. 4.1 Printed Circuit Board Stackup (FR-4 Example)
    2. 4.2 Return Current and Plane References
    3. 4.3 Split Planes – What to Avoid
    4. 4.4 Avoiding Crosstalk
  6. 5 USB Connection
    1. 5.1 Overview
    2. 5.2 Internal Chip Trace Length Mismatch
    3. 5.3 High-Speed Differential Routing
    4. 5.4 SuperSpeed Differential Routing
  7. 6 Package and Breakout
    1. 6.1 Package Drawing
    2. 6.2 Routing Between Pads
    3. 6.3 Pads
    4. 6.4 Land Pattern Recommendation
    5. 6.5 Solder Stencil
  8. 7 PCI Express Connection
    1. 7.1 Internal Chip Trace Length Mismatch
    2. 7.2 Transmit and Receive Links
    3. 7.3 PCI-Express Reference Clock Input
    4. 7.4 PCI Express Reset
    5. 7.5 PCI Express WAKE/CLKREQ
      1. 7.5.1 Leakage Current on Pins WAKE# and CLKREQ#
      2. 7.5.2 Recommendations
  9. 8 Wake from S3
    1. 8.1 Overview
  10. 9 Device Input Clock
    1. 9.1 Overview
  11. 10JTAG Interface
    1. 10.1 Overview
  12. 11Differential Pair ESD Protection
    1. 11.1 Overview
  13. 12SuperSpeed Redriver
    1. 12.1 Overview
  14. 13SMI Pin Implementation
    1. 13.1 Overview
  15. 14Schematics
    1. 14.1 Overview
    2. 14.2 TUSB7320 DEMO EVM REVB Schematics
    3. 14.3 TUSB7340 DEMO EVM REVB Schematics
  16.   Revision History

5.2 Internal Chip Trace Length Mismatch

Routing of the differential pair on the PCB will need to account for length mismatch in the package. This is due to offset pin and the associated bond wire mismatch.

Table 5-1 Length Mismatch

NetName Bondwire Length (mil) Difference (mil)
USB_SSTXN_DN1 96 20
USB_SSTXP_DN1 116
USB_SSRXN_DN1 91 20
USB_SSRXP_DN1 111
USB_DM_DN1 83 22
USB_DP_DN1 105
USB_SSTXP_DN2 104 31
USB_SSTXN_DN2 73
USB_SSRXP_DN2 67 27
USB_SSRXN_DN2 94
USB_DM_DN2 127 34
USB_DP_DN2 93
USB_SSTXP_DN3 73 30
USB_SSTXN_DN3 103
USB_SSRXP_DN3 82 31
USB_SSRXN_DN3 113
USB_DP_DN3 104 34
USB_DM_DN3 138
USB_SSTXP_DN4 58 24
USB_SSTXN_DN4 82
USB_SSRXP_DN4 58 22
USB_SSRXN_DN4 80
USB_DM_DN4 86 26
USB_DP_DN4 60
usb3_usb2_llu149.gifFigure 5-1 USB3 and USB2 Signals from the USB Connector to the Device

Figure 5-2 shows length matching at the device. Length matching must be done at the device side, not at the connector.

length_matching_llu149.gifFigure 5-2 Length Matching