SLAZ759A December   2024  – November 2025 MSPM0L1116 , MSPM0L1117

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Functional Advisories
  5. 2Preprogrammed Software Advisories
  6. 3Debug Only Advisories
  7. 4Fixed by Compiler Advisories
  8. 5Device Nomenclature
  9. 6Advisory Descriptions
    1. 6.1  PMCU_ERR_10
    2. 6.2  PMCU_ERR_11
    3. 6.3  PMCU_ERR_13
    4. 6.4  ADC_ERR_05
    5. 6.5  GPIO_ERR_03
    6. 6.6  I2C_ERR_04
    7. 6.7  I2C_ERR_05
    8. 6.8  I2C_ERR_06
    9. 6.9  I2C_ERR_07
    10. 6.10 I2C_ERR_08
    11. 6.11 I2C_ERR_09
    12. 6.12 I2C_ERR_10
    13. 6.13 UNICOMMI2CC_ERR_01
    14. 6.14 I2C_ERR_13
    15. 6.15 SPI_ERR_04
    16. 6.16 SPI_ERR_05
    17. 6.17 SPI_ERR_06
    18. 6.18 SPI_ERR_07
    19. 6.19 SYSOSC_ERR_01
    20. 6.20 SYSOSC_ERR_02
    21. 6.21 TIMER_ERR_04
    22. 6.22 TIMER_ERR_06
    23. 6.23 TIMER_ERR_06
    24. 6.24 TIMER_ERR_07
    25. 6.25 UART_ERR_01
    26. 6.26 UART_ERR_02
    27. 6.27 UART_ERR_03
    28. 6.28 UART_ERR_04
    29. 6.29 UART_ERR_05
    30. 6.30 UART_ERR_06
    31. 6.31 UART_ERR_07
    32. 6.32 UART_ERR_08
    33. 6.33 UNICOMMUART_ERR_09
    34. 6.34 UART_ERR_11
    35. 6.35 FLASH_ERR_02
    36. 6.36 FLASH_ERR_03
    37. 6.37 FLASH_ERR_05
    38. 6.38 FLASH_ERR_08
    39. 6.39 SYSCTL_ERR_01
    40. 6.40 SYSCTL_ERR_02
    41. 6.41 SYSCTL_ERR_04
    42. 6.42 CPU_ERR_02
    43. 6.43 CPU_ERR_03
    44. 6.44 AES_ERR_01
    45. 6.45 KEYSTORE_ERR_01
    46. 6.46 RST_ERR_01
  10. 7Revision History

6.29 UART_ERR_05

UART Module

Category

Functional

Function

Limitation of debug halt feature in UART module

Description

All Tx FIFO elements are sent out before the communication comes to a halt against the expectation of completing the existing frame and halt.

Workaround

Please make sure data is not written into the TX FIFO after debug halt is asserted.