SLAZ759A December 2024 – November 2025 MSPM0L1116 , MSPM0L1117
I2C Module
Functional
FIFO Read directly after RXDONE interrupt causes erroneous data to be read
When the RXDONE interrupt happens the FIFO is not always updated for the latest data.
Wait 2 I2C CLK cycles for the FIFO to make sure to have the latest data. I2C CLK is based on the CLKSEL register in the I2C registers.