SLAZ759A December 2024 – November 2025 MSPM0L1116 , MSPM0L1117
SPI Module
Functional
SPI underflow event may not generate if read/write to TXFIFO happen at the same time for SPI peripheral
When SPI.CTL0.SPH = 0 and the device is configured as the SPI peripheral.
If there is a write to the TXFIFO WHILE there is a read request from the SPI controller, then an underflow event may not be generated as the read/write request is happening simultaneously.
Ensure the TXFIFO is not empty when the SPI Controller is addressing the device, this can be done by preloading data to avoid a write and read to the same TXFIFO address. Alternatively, data checking strategies, like CRC, can be used to verify the packets were sent properly, then the data can be resent if the CRC doesn't match.