SLAA559E April   2014  – November 2016

 

  1.   Migrating from the MSP430F2xx and MSP430G2xx Families to the MSP430FR58xx/FR59xx/68xx/69xx Family
    1.     Trademarks
    2. 1 Introduction
    3. 2 In-System Programming of Nonvolatile Memory
      1. 2.1 Ferroelectric RAM (FRAM) Overview
      2. 2.2 FRAM Cell
      3. 2.3 Protecting FRAM Using the Memory Protection Unit
        1. 2.3.1 Dynamically Partitioning FRAM
      4. 2.4 FRAM Memory Wait States
      5. 2.5 Bootloader (BSL)
      6. 2.6 JTAG and Security
      7. 2.7 Production Programming
    4. 3 Hardware Migration Considerations
    5. 4 Device Calibration Information
    6. 5 Important Device Specifications
    7. 6 Core Architecture Considerations
      1. 6.1 Power Management Module (PMM)
      2. 6.2 Clock System
      3. 6.3 Operating Modes, Wakeup, and Reset
      4. 6.4 Determining the Cause of Reset
      5. 6.5 Interrupt Vectors
      6. 6.6 FRAM and the FRAM Controller
        1. 6.6.1 Flash and FRAM Overview Comparison
        2. 6.6.2 Cache Architecture
      7. 6.7 RAM Controller (RAMCTL)
    8. 7 Peripheral Considerations
      1. 7.1 Watchdog Timer
      2. 7.2 Ports
        1. 7.2.1 Digital Input/Output
        2. 7.2.2 Capacitive Touch I/O
      3. 7.3 Analog-to-Digital Converters
        1. 7.3.1 ADC12 to ADC12_B
        2. 7.3.2 ADC10 to ADC12_B
      4. 7.4 REF_A Module
      5. 7.5 Comparator_A to Comparator_E
      6. 7.6 Hardware Multiplier (HWMPY32)
      7. 7.7 DMA Controller
      8. 7.8 Low-Energy Accelerator (LEA) for Signal Processing
      9. 7.9 Communication Modules
        1. 7.9.1 USI to eUSCI
        2. 7.9.2 USCI to eUSCI
    9. 8 Conclusion
    10. 9 References
  2.   Revision History

7.2.1 Digital Input/Output

The main differences in the FR59xx general-purpose I/O (GPIO) pins are:

  • All GPIOs have internal configurable pull-up and pull-down resistors.
  • P3 and P4 ports are also interruptible in the FR59xx devices (only P1 and P2 in the F2xx devices)
  • JTAG functionality in the FR59xx devices is multiplexed with GPIO pins on Port J
  • Peripheral function select in the FR59xx devices uses two registers: Port x Function Selection Register 0 (PxSEL0) and Port x Function Selection Register 1 (PxSEL1). These two registers can be set or cleared simultaneously using the Port x Complement Selection Register (PxSELC) to avoid intermediate configurations.

NOTE

GPIOs will not function after reset until this change has been made to firmware.

By default, after BOR, all digital I/O are set as high-impedance with Schmitt triggers and their module functions disabled to prevent any cross current. This enables reduced power consumption when the device starts up.

The following code sequence is required to initialize GPIOs on reset and wakeup from LPMx.5:

  1. Initialize all port pin registers as required for function: Port x Direction Register (PxDIR), Port x Pullup or Pulldown Resistor Enable Register (PxREN), Port x Output Register (PxOUT), Port x Select Register 0 (PxSEL0), Port x Select Register 1 (PxSEL1), and Port x Interrupt Edge Select Register (PxIES).
  2. Clear the LOCKLPM5 bit.
    3. PM5CTL0 &= ~LOCKLPM5
  3. If not waking up from LPMx.5, clear all Port x Interrupt Flag Register (PxIFG) to avoid erroneous port interrupts.
  4. Enable port interrupts using Interrupt Port x Interrupt Enable Register (PxIE).

For more information, see the Configuration After Reset section of the Digital I/O chapter in the MSP430FR58xx, MSP430FR59xx, MSP430FR68xx, and MSP430FR69xx Family User's Guide.