SLAA558A November   2012  – October 2018 MSP430F5212 , MSP430F5214 , MSP430F5217 , MSP430F5219 , MSP430F5222 , MSP430F5224 , MSP430F5229 , MSP430F5252 , MSP430F5253 , MSP430F5254 , MSP430F5255 , MSP430F5256 , MSP430F5257 , MSP430F5258 , MSP430F5259

 

  1.   Designing With MSP430F522x and MSP430F521x Devices
    1.     Trademarks
    2. 1 Split-Supply I/O Systems
    3. 2 DVIO Supplied I/Os
    4. 3 Secondary Digital Functions on DVIO Supplied I/Os
    5. 4 Split-Supply Power-Up or Power-Down Sequence
    6. 5 Reset and NMI Pin Functionality
    7. 6 XT1 and XT2 Oscillators in Bypass Mode
    8. 7 Bootloader (BSL)
      1. 7.1 BSL Entry Sequence for DVIO Supplied BSL Interface
      2. 7.2 BSL Exit Sequence for DVIO Supplied BSL Interface
    9. 8 Debugger Connections
      1. 8.1 JTAG Standard Interface
      2. 8.2 Spy-Bi-Wire Interface
      3. 8.3 Debugging Without DVIO
    10. 9 References
  2.   Revision History

7.1 BSL Entry Sequence for DVIO Supplied BSL Interface

BSLEN is the BSL enable pin with internal pulldown resistor enabled and the BSL entry sequence involves toggling the RST/NMI pin (high-low-high transition) with the BSLEN pin pulled high (see Figure 3).

bsl_entry_sequence_slaa558.gif
A. The minimum timing for this sequence must be within the limits specified for the corresponding pins in the data sheet.
Figure 3. BSL Entry Sequence for DVIO Supplied BSL Interface

Note 2:The BSLEN pin need not be pulled high during the entire period when the device is in BSL mode. However, the BSLEN pin is required to be pulled high for a minimum period of time after the RST/NMI pin goes low-high for proper BSL invoke. See the MSP430F522x, MSP430F521x Mixed-Signal Microcontrollers data sheet for the timing specifications.