SLAA381C December   2007  – September 2018 MSP430F233 , MSP430F235 , MSP430F2410 , MSP430F247 , MSP430F248 , MSP430F249

 

  1.   Migrating From MSP430F13x and MSP430F14x MCUs to MSP430F23x and MSP430F24x MCUs
    1.     Trademarks
    2. 1 Comparison of MSP430F1xx and MSP430F2xx Families
    3. 2 Hardware Considerations for F13x/F14x to F23x/F24x Migration
      1. 2.1 Device Package and Pinout
      2. 2.2 Current Consumption
      3. 2.3 Operating Frequency and Supply Voltage
      4. 2.4 Device Errata
    4. 3 Firmware Considerations for F13x/F14x to F23x/F24x Migration
      1. 3.1 Memory Considerations
        1. 3.1.1 Device Memory Map
        2. 3.1.2 Information Flash Memory
      2. 3.2 Serial Communication – USART and USCI
        1. 3.2.1 UART Mode
        2. 3.2.2 SPI Mode
      3. 3.3 Clock System
        1. 3.3.1 LFXT1 and XT2 Oscillators
        2. 3.3.2 Digitally Controlled Oscillator (DCO)
      4. 3.4 Bootloader (BSL)
      5. 3.5 Interrupt Vectors
      6. 3.6 Beware of Reserved Bits!
      7. 3.7 Timers
      8. 3.8 Analog Comparator
    5. 4 References
  2.   Revision History

3.2.2 SPI Mode

The operation of the F23x/F24x USCI in SPI mode and the F13x/F14x USART is almost identical. The major differences are:

  • The F14x USART supports two channels of simultaneous SPI communication (USART0 and USART1), and the F24x USCI supports four channels (USCI_A0, USCI_B0, USCI_A1, and USCI_B1).
  • The F13x USART supports one channel of SPI communication (USART0), and the F23x USCI supports two channels (USCI_A0 and USCI_B0).
  • On the F14x, each of the four SPI communication endpoints has a dedicated interrupt vector. On the F24x, each USCI module has a two shared interrupt vectors, combining transmit and receive events for each module. On both devices, four interrupt vectors are available in total.
  • On the F13x and on the F23x, each SPI communication endpoint has a dedicated interrupt vector. On both devices, two interrupt vectors are available in total.
  • On the F23x/F24x USCI, interrupt flags are no longer cleared automatically upon entering the interrupt service routine.
  • The F23x/F24x USCI defaults to an LSB-first SPI bit order. The bit order can be configured with the UCMSB bit in the UCAxCTL0/UCBxCTL0 control registers. This is different from the UART module, where the bit order is MSB first and cannot be configured.
  • The maximum F23x/F24x USCI bit clock frequency in SPI master mode is BRCLK, and on the F13x/F14x USART module it is BRCLK/2.