SLAA351A April   2007  – November 2018 MSP430F2232 , MSP430F2232 , MSP430F2234 , MSP430F2234 , MSP430F2252 , MSP430F2252 , MSP430F2254 , MSP430F2254 , MSP430F2272 , MSP430F2272 , MSP430F2274 , MSP430F2274

 

  1.   A Simple Glass-Breakage Detector Using an MSP430™ MCU
    1.     Trademarks
    2. 1 Introduction
    3. 2 Hardware Description
      1. 2.1 Device Specifications
      2. 2.2 Power Supply
      3. 2.3 Microphone
      4. 2.4 LED and Buzzer Alert
      5. 2.5 Interface to CC1100 or CC2500 Devices
      6. 2.6 Operational Amplifiers (OAs)
      7. 2.7 Internal Very-Low-Power Oscillator (VLO)
      8. 2.8 JTAG Interface
      9. 2.9 Current Consumption
    4. 3 Software Description
      1. 3.1 Initialization Routine
      2. 3.2 Timer_A
      3. 3.3 ADC10
      4. 3.4 Signal Analysis
        1. 3.4.1 First Stage of Processing
          1. 3.4.1.1 Signal Averaging, Peak Detection, and Zero Crossings
          2. 3.4.1.2 High-Pass Filtering
        2. 3.4.2 Second Stage of Processing
          1. 3.4.2.1 Frequency Composition Ratio
          2. 3.4.2.2 Peak and Zero-Crossing Count
          3. 3.4.2.3 Glass-Breakage Detect
    5. 4 Hardware Schematic
    6. 5 Test Setup
    7. 6 References
  2.   Revision History

3.1 Initialization Routine

Figure 5 shows a high-level flow diagram of the software execution for initialization of the board. This step occurs at the beginning and after a glass-breakage detect has been issued.

This section of the program initializes all of the peripherals that are needed in the detection routine. The peripherals initialized by this program include Timer_A, CPU clock, ADC10, OAs, and port pins.

The first step is to disable the watchdog timer to avoid an unintended watchdog timer reset. The CPU clock is then set to 8 MHz, and port pins that correspond to the analog inputs are set accordingly. Unused pins are set to outputs, and their values set to high to avoid current consumption. A check on the AAF_select flag is made to enable or disable the AAF. A zero on this flag disables the AAF, and a nonzero value enables it. If this filter is disabled, the input to ADC10 is the output of OA0 and appears at channel A1 of the ADC10. With AAF enabled, the input to ADC10 is the output of OA1, which appears at channel A13 of ADC10. In both cases, the ADC10 is configured with its clock set at SMCLK/3 and for single-conversion mode. Independent of the choice made on the use of AAF, both OA0 and OA1 are configured but not enabled. As mentioned previously, OA0 is configured as an inverting amplifier with a gain of 7 and OA1 as a unity gain buffer. After these initializations are complete, the device enters LPM3, during which time all of the clocks except ACLK (chosen from VLO) are switched off. Timer_A, which is configured to generate an interrupt every 2 ms, wakes the device from this mode.

flowchart_init_laa351.gifFigure 5. Flowchart for Initializations