SFFSB97 April   2026 CD74HC4067-Q1

 

  1.   1
  2.   Trademarks
  3. 1Overview
  4. 2Functional Safety Failure In Time (FIT) Rates
    1. 2.1 DW (SOIC, 24) Package
    2. 2.2 RGY (QFN, 24) Package
    3. 2.3 DGS (VSSOP, 24) Package
    4. 2.4 PW (TSSOP, 24) Package
  5. 3Failure Mode Distribution (FMD)
  6. 4Pin Failure Mode Analysis (Pin FMA)
    1. 4.1 DW (SOIC, 24) Package
    2. 4.2 RGY (QFN, 24) Package
    3. 4.3 DGS (VSSOP, 24) Package
    4. 4.4 PW (TSSOP, 24) Package
  7. 5Revision History

1 Overview

This document contains information for the CD74HC4067-Q1 (DW (SOIC, 24), RGY (QFN, 24), DGS (VSSOP, 24), and PW (TSSOP, 24) packages) to aid in a functional safety system design. Information provided are:

  • Functional safety failure in time (FIT) rates of the semiconductor component estimated by the application of industry reliability standards
  • Component failure modes and distribution (FMD) based on the primary function of the device
  • Pin failure mode analysis (pin FMA)

Figure 1-1 shows the device functional block diagram for reference.

CD74HC4067-Q1 Functional Block DiagramFigure 1-1 Functional Block Diagram

The CD74HC4067-Q1 was developed using a quality-managed development process, but was not developed in accordance with the IEC 61508 or ISO 26262 standards.