SDAA430 June   2026 TAS2118 , TAS2120 , TAS2572 , TAS2574 , TAS2764 , TAS2780 , TAS2781

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Detailed Description
    1. 2.1 Boost over voltage fault considerations for highly inductive speakers
    2. 2.2 Class-D Y-Bridge hysteresis minimum requirement to prevent over current shutdown
    3. 2.3 Class-D Y-Bridge over current shutdown when using EMI filters on the class-D output
  6. 3Summary
  7. 4References

Boost over voltage fault considerations for highly inductive speakers

For highly inductive audio actuators the key problem is that they resist sudden changes in the current through the actuator even if there is a change in the polarity of the voltage through the actuator. Due to this there is a large phase lag between the voltage & the current when driving a highly inductive speaker/haptics actuator. For example, as shown in the following figure, the Class-D amplifier outputs OUT_P & OUT_N are used to drive a full-scale input differential PWM into a speaker coil whose R= 4ohm & L= 1mH with a PVDD supply voltage=13V, as shown in the following equation:

 Class-D outputs connected to inductive speakerFigure 2-1 Class-D outputs connected to inductive speaker
 Example waveform of actuator current when driving a differential PWM showing phase lag between voltage & current across the actuatorFigure 2-2 Example waveform of actuator current when driving a differential PWM showing phase lag between voltage & current across the actuator

As can be observed from the figure, there are scenarios where the Class-D output OUT_P-OUT_N has crossed zero however due to high inductance, the current has a lag in responding to change in the voltage and there is a high negative current of -1.45A.

Due to this phase lag, there are scenarios for certain kinds of input audio files, where if the amplifier is operating at a high peak current and there is a sudden change of phase of the Class-D output the reverse current from the actuator gets pushed into the Boost output through the Class-D FETs. This phenomenon is shown in the image in Figure 2-3. Since boost converters are typically designed to only source an output current & aren't designed to sink any current hence this reverse current ends up overcharging the boost output capacitor to a higher voltage causing the Boost over voltage fault to eventually trigger & shutdown the device.

 Class-D amplifier with integrated boost converter showing the reverse current pathFigure 2-3 Class-D amplifier with integrated boost converter showing the reverse current path
 Class-D amplifier with integrated boost converter showing internal FET current pathFigure 2-4 Class-D amplifier with integrated boost converter showing internal FET current path

The worst-case scenario of such an occurrence, is a large current has built up and suddenly the signal amplitude reduces to a very small value, but the large reverse current causes the boost to charge up and trip an overvoltage. To mimic this scenario, square wave input signals were provided to the amplifier and swept in amplitude from low -9dBFs to -6dBFs to trigger the negative current & OV. Figure 2-5 shows a scope capture of the Boost voltage & speaker current at the time when the OV is triggered due to this kind of audio input to the device with an actuator load of 6ohm+500uH inductance.

 Boost Over voltage fault observed on TAS2572 EVM with default 20uF capacitor with 6ohm+500uH loadFigure 2-5 Boost Over voltage fault observed on TAS2572 EVM with default 20uF capacitor with 6ohm+500uH load

There are 2 Solutions, either of which can be used to avoid Boost Over voltage faults on Integrated boost Class-D amplifier devices with highly inductive loads:

  1. Solution 1: Ensure there is sufficient boost capacitance to prevent the boost inductor current from over-charging the boost capacitor beyond the OV threshold. To calculate the amount of boost capacitance required it must be ensured that the energy stored in the inductor at the worst case peak load current doesn't cause the boost capacitor to over-charge.

    Lets assume the channel gain programmed by the user is "CH" dBV, the speaker resistance is "Rspk" & inductance is "Lspk" and the boost voltage is "Vbst", & the maximum boost voltage OV threshold is "Vov". Let's assume the amplifier has an rdson of Rdson. To calculate the minimum boost capacitance Cmin required to prevent the Boost OV, the follow equations can be applied:

    • The peak voltage across the load (Vpk) = Min(Vbst*Rspk/(Rspk+Rdson), 10^((CH+3)/20))
    • The peak current through the speaker Ipk = Vpk/Rspk
    • Energy stored in the inductor = ½*Lspk*Ipk2
    • To ensure that the energy in the inductor can be dissipated through the capacitor without triggering boost OV fault the ½*C* (Vov2 -Vbst2) > ½*Lspk*Ipk2
    • Cmin (derated) ≥ Lspk*Ipk2/(Vov2 -Vbst2)

    The user must check the appropriate de-rating of the capacitor at DC bias of "Vov" as per the datasheet.

    To ensure that the de-rated capacitance is sufficient to meet the minimum requirement

    To reduce complexity the user may also use the excel sheet calculator included in this TI-E2E post.

     Snapshot of excel calculatorFigure 2-6 Snapshot of excel calculator

    The Cmin (post-derating) & Ipeak highlighted in yellow are the outputs of this excel sheet-based calculator that directly calculates this using the inputs provided by the user. All items not marked in Yellow are inputs to the sheet that must be provided by the user.

    As an example, in the above scenario shown in Figure 6, the load inductance assumed is maximum 500uH & the minimum load impedance assumed is 6.4ohm and the user has programmed the channel gain to 21dBV. The ipeak calculated as output is 1.95A and the minimum capacitance required post-derating to avoid Boost OV trip is ≥21.8uF.

    25V Ceramic capacitors de-rate very heavily at 16V DC bias, hence to realize a ≥21.8uF capacitance this would warrant ≥181uF ceramic capacitance pre-derating, which isn't optimal for cost/footprint.

    To realize this capacitance, it may be more sensible in terms of cost & footprint to utilize:

    • 47uF aluminum electrolytic capacitor (if solution is not height constrained, example Part number: UCM1V470MCL1GS)/ Stacked ceramic capacitors of 50uF (example Part number: ST125C506MAJ10)

    OR

    • 5x10uF capacitors 50V ceramic capacitors (if solution is height constrained, example Part no: GRM21BR61H106ME43L)
  2. Solution 2: Adding a Zener diode voltage clamp on the boost supply to sink the flowback current from the Class-D FET and prevent the boost from triggering OV. This Zener diode voltage tolerance must be relatively low to ensure that it doesn't trigger during normal boost operating conditions but also ensure that the maximum clamping voltage is less than the minimum boost OV threshold. For TAS2572 the boost OV threshold is programmable using: pvdd_ovlo_th_sel[1:0] as per the datasheet for internal boost mode with default set to 16V. Accounting variation of ±2% the minimum threshold is 15.68V. Hence it must be ensured that the Zener diode must activate only >13V & <15.86V. So, either a 14V or 15V Zener diode can be used with +-5% tolerance. (example part number: 4878-SZ3C15). Ensure the power rating of the Zener diode is sufficient to tolerate high currents for short duration.