--define=_BOOT_SIZE_=(8*1024)

MEMORY
{
    FLASH_BOOT      (RX)  : origin = 0x00000000,  length = _BOOT_SIZE_
    FLASH_APP       (RX)  : origin = _BOOT_SIZE_, length = (0x00040000 - _BOOT_SIZE_)
}

SECTIONS
{
    .intvecs      : > 0x00000000
    .text         : palign(8) {} > FLASH_BOOT
    .const        : palign(8) {} > FLASH_BOOT
    .cinit        : palign(8) {} > FLASH_BOOT
    .pinit        : palign(8) {} > FLASH_BOOT
    .rodata       : palign(8) {} > FLASH_BOOT
    .ARM.exidx    : palign(8) {} > FLASH_BOOT
    .init_array   : palign(8) {} > FLASH_BOOT
    .binit        : palign(8) {} > FLASH_BOOT
}

The CSC boundary is set to 8,192 bytes (0x0000 ~ 0x2000). Users must align the boundary to 0x400 due to the Arm Cortex-M0+ VTOR (Vector Table Offset Register) alignment requirement of 0x100 and the flash erase sector size of 1 kB (0x400).