SBOK079 October   2023 TPS7H2140-SEP

PRODUCTION DATA  

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1 Introduction
  5. 2 Single-Event Effects (SEE)
  6. 3 Device and Test Board Information
  7. 4 Irradiation Facility and Setup
  8. 5 Depth, Range, and LETEFF Calculation
  9. 6 Test Setup and Procedures
  10. 7 Destructive Single-Event Effects (DSEE)
    1. 7.1 Single-Event Latch-up (SEL) Results
    2. 7.2 Single-Event Burnout (SEB) and Single-Event Gate Rupture (SEGR) Results
  11. 8 Single-Event Transients (SET)
  12. 9 Event Rate Calculations
  13. 10Summary
  14. 11References

2 Single-Event Effects (SEE)

The primary concern for the TPS7H2140-SEP is the robustness against the destructive single-event effects (DSEE), single-event latch-up (SEL), single-event burnout (SEB), and single-event gate rupture (SEGR). In mixed technologies such as the BiCMOS process used on the TPS7H2140-SEP, the CMOS circuitry introduces a potential for SEL susceptibility.

SEL can occur if excess current injection caused by the passage of an energetic ion is high enough to trigger the formation of a parasitic cross-coupled PNP and NPN bipolar structure, which is formed between the p-sub and n-well and n+ and p+ contacts. (For more information, see [1 and 2]). The parasitic bipolar structure initiated by a single-event creates a high-conductance path (inducing a steady-state current that is typically orders-of-magnitude higher than the normal operating current) between power and ground that persists (is “latched”) until power is removed, the device is reset, or until the high-current state destroys the device. The TPS7H2140-SEP was tested for SEL at the maximum recommended voltage of 32 V and maximum load current of 5.4 A (1.35 A per channel). The device was set up with OUT1 operating in a single configuration. OUT2, OUT3, and OUT4 were operated in a parallel configuration. See Figure 6-1 for more details. The device did not exhibit SEL when heavy-ions with LETEFF = 48 MeV × cm2 / mg at flux ≈105 ions / cm2× s, fluences of ≈107 ions / cm2, and a die temperature of 125°C.

Since this device is designed to conduct large currents up to 5.4 A (1.35 A per channel) and can withstand up to 32 V during the off-state, the power LDMOS introduces a potential susceptibility for SEB and SEGR (2). The TPS7H2140-SEP was evaluated for SEB and SEGR at full load conditions of 5.4 A (1.35 A per channel), and a maximum voltage of 32 V in both the enabled and disabled modes. During SEB and SEGR testing, a single current event was not observed, demonstrating that the TPS7H2140-SEP is SEB and SEGR-free up to LETEFF = 48 MeV·cm2/ mg at a flux of ≈105 ions / cm2 × s, fluences of ≈107 ions / cm2, and a die temperature of ≈25°C.

The TPS7H2140-SEP was characterized for SET at a flux of ≈105 ions / cm2·s, fluences of ≈107 ions / cm2, and at room temperature. The device was characterized at IN = 4.5 V at a load of 2 A (0.5-A per channel) load. Under these conditions, the device showed three different single-event transients (SET) signatures under heavy-ion irradiation. All observed types of SETs were self-recoverable without requiring external intervention. The observed transients can be classified as:

  1. A brief transient of the output voltage (referred here as OUTX,SET). For the purpose of this report the transients were characterize for deviations –3% ≤ OUTX ≤ 3% from the nominal output voltage. For more details, see Section 8.
  2. A brief transient on the Current Sense (CS) pin. For the purpose of this report the transients were characterized for deviations –4% ≤ CS ≤ 4% from the nominal output voltage. This type of SET is referred to here as CSSET.
  3. A FAULT upset ≥ 1 V from nominal on a negative-edge trigger.