SBAU412A November   2022  – May 2024 AFE7900 , AFE7903 , AFE7906 , AFE7920 , AFE7921 , AFE7950

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. Introduction
  5. Prerequisites
  6. Typical Bare-Metal Design Flow
  7. Background
  8. Add Microblaze and SPI IP for Use in Vitis for Embedded Development
  9. Create New Platforms in Vitis
  10. Create New Application Projects in Vitis
  11. Build Application Projects
  12. Generate SPI Log for AFE79xx EVM
    1. 9.1 Generating the LMK SPI Log
    2. 9.2 Generating the AFE SPI Log
    3. 9.3 Converting SPI Logs to Format for Vitis
  13. 10AFE79xxEVM Board Modifications
  14. 11Configure the AXI GPIO
    1. 11.1 Initializing the GPIO
    2. 11.2 Setting the Direction
    3. 11.3 Setting High or Low for Corresponding Bits
  15. 12Configure the AXI SPI
  16. 13Set Up and Power on Hardware
  17. 14Set up ZCU102 Board Interface for VADJ_FMC
  18. 15Debug Application Projects and Set up Vitis Serial Terminal
  19. 16Execute the Application
  20. 17Revision History

Configure the AXI SPI

The AXI SPI instance in TI AFE SPI IP is used in Standard Mode.

Peripherals select 0 and select 1 are used as chip selects for AFE and LMK clocking device, respectively

SCL frequency is hard coded to 10 MHz within TI IP

Key commands for SPI initialization and usage in Vitis are as explained below:

  1. XSpi_Config *ConfigPtr;

    Initialize a pointer (ConfigPtr).

  2. ConfigPtr = XSpi_LookupConfig(XPAR_AXI_QUAD_SPI_0_DEVICE_ID);

    Refer ‘Xparameters.h’ to find the correct AXI QUAD SPI DEVICE ID.

  3. XSpi_CfgInitialize(&Spidev, ConfigPtr, ConfigPtr->BaseAddress);

    Initialize a new instance of SPI (Spidev).

  4. XSpi_SetOptions(&Spidev, XSP_MASTER_OPTION);

    Set the Spidev instance to be in Controller mode.

  5. XSpi_Start(&Spidev);
  6. XSpi_SetSlaveSelect(&Spidev, 1);

    Select Peripheral: AFE.

  7. XSpi_SetSlaveSelect(&Spidev, 2);

    Select Peripheral: LMK.

  8. XSpi_Transfer(&Spidev, WrBufdev, RdBufdev, 3);

    Second argument WrBufdev is an array with 3 bytes (24-bit data to be transmitted on SPI).

    Third argument RdBufdev is an array with 3 bytes, the last byte has the SPI read value.

    Fourth argument is number of bytes to be transmitted/received...3 in our case.

The D23 is the MSB bit of the 24-bit data because the D23 indicates whether it is a Read or a Write SPI operation:

  • If D23 is set to 1, then it is a read operation and RdBufdev[2] stores the read back address contents
  • If D23 is set to 0, then it is a write operation and RdBufdev[2] has no significance