SBAS741B October 2015 – April 2020
PRODUCTION DATA.
The chip select pin (CS) selects the ADS1018-Q1 for SPI communication. This feature is useful when multiple devices share the same serial bus. Keep CS low for the duration of the serial communication. When CS is taken high, the serial interface is reset, SCLK is ignored, and DOUT/DRDY enters a high-impedance state. In this state, DOUT/DRDY cannot provide data-ready indication. In situations where multiple devices are present and DOUT/DRDY must be monitored, lower CS periodically. At this point, the DOUT/DRDY pin either immediately goes high to indicate that no new data are available, or immediately goes low to indicate that new data are present in the Conversion register and are available for transfer. New data can be transferred at any time without concern of data corruption. When a transmission starts, the current result is locked into the output shift register and does not change until the communication completes. This system avoids any possibility of data corruption.