SBAS741B October 2015 – April 2020
PRODUCTION DATA.
If Config register data are not required to be read back, the ADS1018-Q1 conversion data can be clocked out in a short 16-bit data transmission cycle, as shown in Figure 15. Take CS high after the 16th SCLK cycle to reset the SPI interface. The next time CS is taken low, data transmission starts with the currently buffered conversion result on the first SCLK rising edge. If DOUT/DRDY is low when data retrieval starts, the conversion buffer is already updated with a new result. Otherwise, if DOUT/DRDY is high, the same result from the previous data transmission cycle is read.