F28377D-SEP integrates with high-speed synchronous SPI that allows a serial bit stream of programmed length (1 to 16 bits) to be shifted into and out of the device, furthermore, it supports a 16-level receive and transmit FIFO.

In this interfacing scheme, the SPI port is configured as a slave device with 4-wire mode operation. For compatibility with ADC168M102R-SEP timing diagram, the SPI port is set to output data on rising edge and input data on falling edge with non-delayed clock.

In the source code, the character length of the SPI port is set as 11 bits, a buffer is employed in the transmission and reception, the next word in the buffer is transferred immediately upon completion of transmission of the previous one, thus combining two SPI transmissions into one ADC168M102R-SEP conversion cycle; the following several lines of code shows the translation between them. Table 4-2 lists the key register settings of the SPI port previously described.

1.One ADC168M102R-SEP configure command split into two SPI transmission cycles:
        for(Cnt=0; Cnt < number; Cnt++)
        {
           SpiaRegs.SPITXBUF = (*(data+Cnt) >> 1) & 0x7FE0 ;
           SpiaRegs.SPITXBUF = (*(data+Cnt) << 10) & 0xFC00;
        }

2. Two SPI reception cycles combine together to be one ADC168M102R-SEP conversion result:
        for(Counteri = 0; Counteri < Rxcounter/2; Counteri ++ )
        {
           RxInterpreter[Counteri] = ( Rxdata[Counteri * 2] << 6 ) 
                                        | ( Rxdata[Counteri * 2 +1] >> 5 );
        }

The two ePWM modules used is set to clock at the same rate and counter mode, with different counter period so that they could be used as RD/CONVST signal or clock signal. The counter value of ePWM2 module is synchronized to be zero when the counter value of ePWM1 module reaches to zero. Key register setting for ePWM module is shown in Table 4-3.