SBAA804 April   2026 ADC168M102R-SEP

 

  1.   1
  2.   Abstract
  3. 1Introduction
  4. 2Hardware Platform
  5. 3Hardware Interfaces
    1. 3.1 Communication via McBSP
      1. 3.1.1 Using McBSP1
      2. 3.1.2 Channel Identification
    2. 3.2 Communication via SPI and ePWM
      1. 3.2.1 Using SPI and ePWM
      2. 3.2.2 SPI Peripheral Requirement
  6. 4Software Interface
    1. 4.1 McBSP Settings
    2. 4.2 SPI and ePWM Settings
    3. 4.3 Software Flow
  7. 5Summary
  8. 6References

4.1 McBSP Settings

The McBSP is programmed as a serial port with the internal sample rate generator (SRG) configured to generate the internal data clock (CLKG), which is used as internal transmit clock (CLKX). The transmitter and receiver are set as 16-bit operation with a one-bit delay after frame synchronization and before the transmission/reception of the first bit of the frame.

The transmit frame-synchronization pulse (FSX) is generated by the SRG, the width of the FSX should be set as one CLKX clock cycle. Depending on whether the polling or interrupt mechanism is used to process the transmission and reception data, the FSX needs to be set as: (1) generated when the transmit register is written or (2) periodically based on the setting of FPER bits in SRGR2 register. Table 4-1 lists the key register settings of McBSP interfacing with the ADC168M102R-SEP using polling or interrupt methodology.

Table 4-1 Key Register Setting of McBSP
RegisterSetting for Polling OperationSetting for Interrupt OperationComments
SRGR2.bit.CLKSM11SRG use LSPCLK as input clock
PCR.bit.SCLKME00
SRGR1.bit.CLKGDV99Clock divider
PCR.bit.CLKXM11CLKX is driven by CLKG
RCR1.bit.RWDLEN122Set as 16-bit operation
XCR1.bit.XWDLEN122
RCR2.bit.RDATDLY11one-bit delay on data receive and transmit
XCR2.bit.XDATDLY11
PCR.bit.FSXM11FSX is driven by CLKG
SRGR1.bit.FWID00FSX is 1 CLKG cycle width
SRGR2.bit.FSGM00Different ways to generate FSX
SRGR2.bit.FPER–21Period between two FSX signal
MFFINT.bit.XINT–1Enable Tx/Rx interrupt.
MFFINT.bit.RINT–1

In the sample code, the ADC168M102R-SEP is running with a serial clock of 20 MHz, which is achieved by divide ten from low-speed peripheral clock (LSPCLK). The fixed data rate continuous conversion of ADC168M102R-SEP is realized by using interrupt mechanism to process the data in McBSP, while the ADC168M102R-SEP is configured using polling mechanism to process the data in McBSP, shown as the following lines of code.

    for(loopcount = 0; loopcount<5; loopcount ++)
    {
        mcbsp_xmit(Txdata[Txcounter++],0);
        while(McbspaRegs.SPCR1.bit.RRDY == 0 ) { ; }   // Check for receive available?
        Rxdata[Rxcounter++] = McbspaRegs.DRR1.all;     // read out result.
        while(McbspaRegs.SPCR2.bit.XRDY == 0){ ; }    // Check for transmit ready?
    }