The ADC168M102R-SEP needs at least 20 clock cycles to finish one conversion cycle. To ensure the conversion accuracy or maintain the constant conversion speed, it would be helpful if the SPI peripheral used here has the capability of handling at least 20 bits of data size or integrates with transmit and receive buffers. Otherwise, the software implementation should specify that the idle time between the two conversion portion, t_idle, is less than the maximum clock period (2 µs in the ADC168M102R-SEP while operating at half-clock mode). Figure 3-8 shows the waveform using an 8-bit SPI without transmit and receive buffer interfacing to the ADC168M102R-SEP.

Figure 3-8 Interfacing to ADC168M102R-SEP with an 8-bit SPI without Buffer