SBOS407D December   2007  – May 2016 VCA821

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics: VS = ±5 V
    6. 7.6  Typical Characteristics: VS = ±5 V, DC Parameters
    7. 7.7  Typical Characteristics: VS = ±5 V, DC and Power-Supply Parameters
    8. 7.8  Typical Characteristics: VS = ±5 V, AVMAX = 6 dB
    9. 7.9  Typical Characteristics: VS = ±5 V, AVMAX = 20 dB
    10. 7.10 Typical Characteristics: VS = ±5 V, AVMAX = 32 dB
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Feature Description
    3. 9.3 Device Functional Modes
      1. 9.3.1 Maximum Gain of Operation
      2. 9.3.2 Output Current and Voltage
      3. 9.3.3 Input Voltage Dynamic Range
      4. 9.3.4 Output Voltage Dynamic Range
      5. 9.3.5 Bandwidth
      6. 9.3.6 Offset Adjustment
      7. 9.3.7 Noise
        1. 9.3.7.1 Input and ESD Protection
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Design-In Tools
        1. 10.1.1.1 Demonstration Boards
        2. 10.1.1.2 Macromodels and Applications Support
        3. 10.1.1.3 Operating Suggestions
        4. 10.1.1.4 Package Considerations
    2. 10.2 Typical Applications
      1. 10.2.1 Wideband Variable-Gain Amplifier Operation Application
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedure
        3. 10.2.1.3 Application Curve
      2. 10.2.2 Difference Amplifier Application
        1. 10.2.2.1 Design Requirements
        2. 10.2.2.2 Detailed Design Procedure
        3. 10.2.2.3 Application Curve
      3. 10.2.3 Differential Equalizer Application
        1. 10.2.3.1 Design Requirements
        2. 10.2.3.2 Detailed Design Procedure
        3. 10.2.3.3 Application Curve
      4. 10.2.4 Differential Cable Equalizer Application
        1. 10.2.4.1 Design Requirements
        2. 10.2.4.2 Detailed Design Procedure
        3. 10.2.4.3 Application Curve
      5. 10.2.5 AGC Loop Application
        1. 10.2.5.1 Design Requirements
        2. 10.2.5.2 Detailed Design Procedure
    3. 10.3 System Examples
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
    3. 12.3 Thermal Considerations
  13. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 Third-Party Products Disclaimer
    2. 13.2 Community Resources
    3. 13.3 Trademarks
    4. 13.4 Electrostatic Discharge Caution
    5. 13.5 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

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12 Layout

12.1 Layout Guidelines

Achieving optimum performance with a high-frequency amplifier such as the VCA821 device requires careful attention to printed circuit board (PCB) layout parasitics and external component types. Recommendations to optimize performance include the following:

  1. Minimize parasitic capacitance to any AC ground for all of the signal I/O pins. This recommendation includes GND (pin 2). Parasitic capacitance on the output can cause instability on both the inverting input and the noninverting input, and it can react with the source impedance to cause unintentional band limiting. To reduce unwanted capacitance, a window around the signal I/O pins must be opened in all of the ground and power planes around those pins. Otherwise, ground and power planes must be unbroken elsewhere on the board. Place a small series resistance (greater than 25 Ω) with the input pin connected to ground to help decouple package parasitics.
  2. Minimize the distance (less than 0.25 inches, or 6.3 mm) from the power-supply pins to high-frequency 0.1-μF decoupling capacitors. At the device pins, the ground and power plane layout must not be in close proximity to the signal I/O pins. Avoid narrow power and ground traces to minimize inductance between the pins and the decoupling capacitors. The power-supply connections must always be decoupled with these capacitors. Larger decoupling capacitors (2.2 μF to 6.8 μF), effective at lower frequencies, must also be used on the main supply pins. These capacitors can be placed somewhat farther from the device and may be shared among several devices in the same area of the PCB.
  3. Careful selection and placement of external components preserves the high-frequency performance of the VCA821 device. Resistors must be a very low-reactance type. Surface-mount resistors work best and allow a tighter overall layout. Metal-film and carbon composition, axially-leaded resistors can also provide good high-frequency performance. Again, keep the leads and PCB trace length as short as possible. Never use wire-wound type resistors in a high-frequency application. Because the output pin is the most sensitive to parasitic capacitance, always position the series output resistor, if any, as close as possible to the output pin. Other network components, such as inverting or noninverting input termination resistors, must also be placed close to the package.
  4. Connections to other wideband devices on the board may be made with short direct traces or through onboard transmission lines. For short connections, consider the trace and the input to the next device as a lumped capacitive load. Relatively wide traces (50 mils to 100 mils, or 1.27 mm to 2.54 mm) must be used, preferably with ground and power planes opened up around them.
  5. Socketing a high-speed part like the VCA821 device is not recommended. The additional lead length and pin-to-pin capacitance introduced by the socket can create an extremely troublesome parasitic network, which can make it almost impossible to achieve a smooth, stable frequency response. Best results are obtained by soldering the VCA821 device onto the board.

12.2 Layout Example

VCA821 layout_sbos395.png Figure 90. Layout Recommendations

12.3 Thermal Considerations

The VCA821 device does not require heat sinking or airflow in most applications. The maximum desired junction temperature sets the maximum allowed internal power dissipation as described in this section. The maximum junction temperature must not exceed 150°C.

Operating junction temperature (TJ) is given by Equation 6.

Equation 6. VCA821 q_tj_bos407.gif

The total internal power dissipation (PD) is the sum of quiescent power (PDQ) and additional power dissipated in the output stage (PDL) to deliver load power. Quiescent power is simply the specified no-load supply current times the total supply voltage across the part. PDL depends on the required output signal and load; for a grounded resistive load; however, it is at a maximum when the output is fixed at a voltage equal to one-half of either supply voltage (for equal bipolar supplies). Under this worst-case condition, PDL = VS 2 / (4 × RL), where RL is the resistive load.

NOTE

It is the power in the output stage and not in the load that determines internal power dissipation.

As a worst-case example, compute the maximum TJ using a VCA821ID (SOIC-14 package) in the circuit of Figure 79 operating at maximum gain and at the maximum specified ambient temperature of 85°C.

Equation 7. VCA821 q_pd_bos407.gif
Equation 8. VCA821 q_max_tj_bos407.gif

This maximum operating junction temperature is well below most system level targets. Most applications must be lower because an absolute worst-case output stage power was assumed in this calculation of VCC / 2, which is beyond the output voltage range for the VCA821 device.