ZHCSBB1D July 2013 – March 2018 UCC28740
The capacitance on VDD must supply the primary-side operating current used during startup and between low-frequency switching pulses. The largest result of three independent calculations denoted in Equation 27, Equation 28, and Equation 29 determines the value of CVDD.
At startup, when VVDD(on) is reached, CVDD alone supplies the device operating current and MOSFET gate current until the output of the converter reaches the target minimum-operating voltage in CC regulation, VOCC. Now the auxiliary winding sustains VDD for the UCC28740 above UVLO. The total output current available to the load and to charge the output capacitors is the CC-regulation target, IOCC. Equation 27 assumes that all of the output current of the converter is available to charge the output capacitance until VOCC is achieved. For typical applications, Equation 27 includes an estimated qGfSW(max) of average gate-drive current and a 1-V margin added to VVDD.
During a worst-case un-load transient event from full-load to no-load, COUT overcharges above the normal regulation level for a duration of tOV, until the output shunt-regulator loading is able to drain VOUT back to regulation. During tOV, the voltage feedback loop and optocoupler are saturated, driving maximum IFB and temporarily switching at fSW(min). The auxiliary bias current expended during this situation exceeds that normally required during the steady-state no-load condition. Equation 28 calculates the value of CVDD (with a safety factor of 2) required to ride through the tOV duration until steady-state no-load operation is achieved.
Finally, in the steady-state no-load operating condition, total no-load auxiliary-bias current, IAUXNL is provided by the converter switching at a no-load frequency, fSWNL, which is generally higher than fSW(min). CVDD is calculated to maintain a target VDD ripple voltage lower than ΔVVDD, using Equation 29.