ZHCSBB1D July   2013  – March 2018 UCC28740

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
    1.     Device Images
      1.      简化应用示意图
      2.      典型伏安图
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Detailed Pin Description
      2. 7.3.2 Valley-Switching and Valley-Skipping
      3. 7.3.3 Startup Operation
      4. 7.3.4 Fault Protection
    4. 7.4 Device Functional Modes
      1. 7.4.1 Secondary-Side Optically Coupled Constant-Voltage (CV) Regulation
      2. 7.4.2 Primary-Side Constant-Current (CC) Regulation
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Custom Design With WEBENCH® Tools
        2. 8.2.2.2 Standby Power Estimate and No-Load Switching Frequency
        3. 8.2.2.3 Input Bulk Capacitance and Minimum Bulk Voltage
        4. 8.2.2.4 Transformer Turns-Ratio, Inductance, Primary Peak Current
        5. 8.2.2.5 Transformer Parameter Verification
        6. 8.2.2.6 VS Resistor Divider, Line Compensation
        7. 8.2.2.7 Output Capacitance
        8. 8.2.2.8 VDD Capacitance, CVDD
        9. 8.2.2.9 Feedback Network Biasing
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 VDD Pin
      2. 10.1.2 VS Pin
      3. 10.1.3 FB Pin
      4. 10.1.4 GND Pin
      5. 10.1.5 CS Pin
      6. 10.1.6 DRV Pin
      7. 10.1.7 HV Pin
    2. 10.2 Layout Example
  11. 11器件和文档支持
    1. 11.1 器件支持
      1. 11.1.1 开发支持
        1. 11.1.1.1 使用 WEBENCH® 工具定制设计方案
      2. 11.1.2 器件命名规则
        1. 11.1.2.1  电容术语（以法拉为单位）
        2. 11.1.2.2  占空比术语
        3. 11.1.2.3  频率术语（以赫兹为单位）
        4. 11.1.2.4  电流术语（以安培为单位）
        5. 11.1.2.5  电流和电压调节术语
        6. 11.1.2.6  变压器术语
        7. 11.1.2.7  功率术语（以瓦特为单位）
        8. 11.1.2.8  电阻术语（以 Ω 为单位）
        9. 11.1.2.9  时序术语（以秒为单位）
        10. 11.1.2.10 电压术语（以伏特为单位）
        11. 11.1.2.11 交流电压术语（以 VRMS 为单位）
        12. 11.1.2.12 效率术语
    2. 11.2 文档支持
      1. 11.2.1 相关文档
    3. 11.3 接收文档更新通知
    4. 11.4 社区资源
    5. 11.5 商标
    6. 11.6 静电放电警告
    7. 11.7 Glossary
  12. 12机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

6.5 Electrical Characteristics

over operating free-air temperature range, VVDD = 25 V, HV = open, VFB = 0 V, VVS = 4 V, TA = –40°C to +125°C, TJ = TA (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
HIGH-VOLTAGE START UP
IHV Start-up current out of VDD VHV = 100 V, VVDD = 0 V, start state 100 250 500 µA
IHVLKG25 Leakage current at HV VHV = 400 V, run state, TJ = 25°C 0.01 0.5 µA
BIAS SUPPLY INPUT
IRUN Supply current, run IDRV = 0, run state 2 2.65 mA
IWAIT Supply current, wait IDRV = 0, wait state 95 125 µA
ISTART Supply current, start IDRV = 0, VVDD = 18 V, start state, IHV = 0 18 30 µA
IFAULT Supply current, fault IDRV = 0, fault state 95 130 µA
UNDERVOLTAGE LOCKOUT
VVDD(on) VDD turnon threshold VVDD low to high 19 21 23 V
VVDD(off) VDD turnoff threshold VVDD high to low 7.35 7.75 8.15 V
VS INPUT
VVSNC Negative clamp level IVSLS = –300 µA, volts below ground 190 250 325 mV
IVSB Input bias current VVS = 4 V –0.25 0 0.25 µA
FB INPUT
IFBMAX Full-range input current fSW = fSW(min) 16 23 30 µA
VFBMAX Input voltage at full range IFB = 25 µA, TJ = 25°C 0.75 0.88 1 V
RFB FB-input resistance, linearized ΔIFB = 20 µA, centered at IFB = 15 µA, TJ = 25°C 10 14 18 kΩ
CS INPUT
VCST(max) Maximum CS threshold voltage IFB = 0 µA(1) 738 773 810 mV
VCST(min) Minimum CS threshold voltage IFB = 35 µA(1) 170 194 215 mV
KAM AM-control ratio VCST(max) / VCST(min) 3.6 4 4.45 V/V
VCCR Constant-current regulation factor 318 330 343 mV
KLC Line-compensation current ratio IVSLS = –300 µA, IVSLS / current out of CS pin 24 25 28.6 A/A
tCSLEB Leading-edge blanking time DRV output duration, V CS = 1 V 180 230 280 ns
DRIVERS
IDRS DRV source current VDRV = 8 V, VVDD = 9 V 20 25 mA
RDRVLS DRV low-side drive resistance IDRV = 10 mA 6 12 Ω
VDRCL DRV clamp voltage VVDD = 35 V 14 16 V
RDRVSS DRV pulldown in start-state 150 190 230 kΩ
PROTECTION
VOVP Overvoltage threshold At VS input, TJ = 25°C(2) 4.52 4.6 4.71 V
VOCP Overcurrent threshold At CS input 1.4 1.5 1.6 V
IVSL(run) VS line-sense run current Current out of VS pin increasing 190 225 275 µA
IVSL(stop) VS line-sense stop current Current out of VS pin decreasing 70 80 100 µA
KVSL VS line sense ratio IVSL(run) / IVSL(stop) 2.45 2.8 3.05 A/A
TJ(stop) Thermal-shutdown temperature Internal junction temperature 165 °C
(1) This device automatically varies the control frequency and current sense thresholds to improve EMI performance. These threshold voltages and frequency limits represent average levels.
(2) The overvoltage threshold level at VS decreases with increasing temperature by 0.8 mV/°C. This compensation is included to reduce the power-supply output overvoltage detection variance over temperature.