SLUSDW0B May   2020  – May 2020 UCC28065

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Simplified Application
  4. 4 Revision History
  5. 5 Description (Continued)
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Principles of Operation
      2. 8.3.2  Natural Interleaving
      3. 8.3.3  On-Time Control, Maximum Frequency Limiting, Restart Timer and Input Voltage Feed-Forward compensation
      4. 8.3.4  Zero-Current Detection and Valley Switching
      5. 8.3.5  Phase Management and Light-Load Operation
      6. 8.3.6  Burst Mode Operation
      7. 8.3.7  External Disable
      8. 8.3.8  Improved Error Amplifier
      9. 8.3.9  Soft Start
      10. 8.3.10 Brownout Protection
      11. 8.3.11 Line Dropout Detection
      12. 8.3.12 VREF
      13. 8.3.13 VCC
      14. 8.3.14 System Level Protections
        1. 8.3.14.1 Failsafe OVP - Output Over-voltage Protection
        2. 8.3.14.2 Overcurrent Protection
        3. 8.3.14.3 Open-Loop Protection
        4. 8.3.14.4 VCC Undervoltage Lock-Out (UVLO) Protection
        5. 8.3.14.5 Phase-Fail Protection
        6. 8.3.14.6 CS - Open, TSET - Open and Short Protection
        7. 8.3.14.7 Thermal Shutdown Protection
        8. 8.3.14.8 Fault Logic Diagram
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1  Inductor Selection
        2. 9.2.2.2  ZCD Resistor Selection RZA, RZB
        3. 9.2.2.3  HVSEN
        4. 9.2.2.4  Output Capacitor Selection
        5. 9.2.2.5  Selecting RS For Peak Current Limiting
        6. 9.2.2.6  Power Semiconductor Selection (Q1, Q2, D1, D2)
        7. 9.2.2.7  Brownout Protection
        8. 9.2.2.8  Converter Timing
        9. 9.2.2.9  Programming VOUT
        10. 9.2.2.10 Voltage Loop Compensation
      3. 9.2.3 Application Curves
        1. 9.2.3.1 Input Ripple Current Cancellation with Natural Interleaving
        2. 9.2.3.2 Brownout Protection
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information
    1. 13.1 Package Option Addendum
      1. 13.1.1 Packaging Information

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

7.6 Typical Characteristics

VVCC = 16 V, VAGND = VPGND = 0 V, VVINAC = 3 V, VVSENSE = 6 V, VHVSEN = 3 V, VPHB = 0 V, RTSET = 133 kΩ; all voltages are with respect to GND, all outputs unloaded, TJ = 25°C, and currents are positive into and negative out of the specified terminal, unless otherwise noted.
UCC28065 D001_SLUSDW0.gif
Figure 1. Minimum Period vs. RTSET Resistance
UCC28065 D102SLUA789.gif
Figure 3. VINAC Brownout Hysteresis Current
UCC28065 D104SLUA789.gif
Figure 5. UVLO On Off Thresholds
UCC28065 D106SLUA789.gif
Figure 7. VCC Bias Supply Current
UCC28065 Figure_06_slusao7.gif
Figure 9. Error Amplifier Transconductance vs VSENSE
UCC28065 Figure_08_slusao7.gif
Figure 11. Error Amplifier Output Current vs Output Voltage
UCC28065 tc_gate_fall-t_lus837.gif
CLOAD = 4.7 nF
Figure 13. Gate Drive Falling vs Time
UCC28065 tc_gate_fall-t_delay_lus837.gif
CLOAD = 4.7 nF
Figure 15. Gate Drive Falling and Delay From CS Input vs Time
UCC28065 D101SLUA789.gif
Figure 2. VINAC Brownout Detection Threshold
UCC28065 D103SLUA789.gif
Figure 4. VREF Output Voltage
UCC28065 D105SLUA789.gif
Figure 6. UVLO Hysteresis
UCC28065 eaiout_vs_vsensevin_slusde9.gif
Soft-start period completed
Figure 8. Error Amplifier Output Current vs Input Voltage
UCC28065 Figure_07_slusao7.gif
Figure 10. Error Amplifier Transconductance vs Temperature
UCC28065 tc_gate_rise-t_lus837.gif
CLOAD = 4.7 nF
Figure 12. Gate Drive Rising vs Time
UCC28065 tc_gate_rise-t_delay_lus837.gif
CLOAD = 4.7 nF
Figure 14. Gate Drive Rising and Delay From ZCD Input vs Time