SLUS828D December   2008  – October 2017 UCC28019A

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Soft-Start
      2. 7.3.2  System Protection
        1. 7.3.2.1  VCC Undervoltage Lockout (UVLO)
        2. 7.3.2.2  Input Brown-Out Protection (IBOP)
        3. 7.3.2.3  Output Overvoltage Protection (OVP)
        4. 7.3.2.4  Open Loop Protection/Standby (OLP/Standby)
        5. 7.3.2.5  ISENSE Open-Pin Protection (ISOP)
        6. 7.3.2.6  Output Undervoltage Detection (UVD) and Enhanced Dynamic Response (EDR)
        7. 7.3.2.7  Over-Current Protection
        8. 7.3.2.8  Soft Over Current (SOC)
        9. 7.3.2.9  Peak Current Limit (PCL)
        10. 7.3.2.10 Current Sense Resistor, RISENSE
      3. 7.3.3  Gate Driver
      4. 7.3.4  Current Loop
      5. 7.3.5  ISENSE and ICOMP Functions
      6. 7.3.6  Pulse Width Modulator
      7. 7.3.7  Control Logic
      8. 7.3.8  Voltage Loop
      9. 7.3.9  Output Sensing
      10. 7.3.10 Voltage Error Amplifier
      11. 7.3.11 Non-Linear Gain Generation
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Current Calculations
        2. 8.2.2.2  Bridge Rectifier
        3. 8.2.2.3  Input Capacitor
        4. 8.2.2.4  Boost Inductor
        5. 8.2.2.5  Boost Diode
        6. 8.2.2.6  Switching Element
        7. 8.2.2.7  Sense Resistor
        8. 8.2.2.8  Output Capacitor
        9. 8.2.2.9  Output Voltage Set Point
        10. 8.2.2.10 Loop Compensation
        11. 8.2.2.11 Brown Out Protection
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
    1. 9.1 Bias Supply
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Related Products
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

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10 Layout

10.1 Layout Guidelines

As with all PWM controllers, the effectiveness of the filter capacitors on the signal pins depends upon the integrity of the ground return. The pin out of the UCC28019A is ideally suited for separating the high di/dt induced noise on the power ground from the low current quiet signal ground required for adequate noise immunity. A star point ground connection at the GND pin of the device can be achieved with a simple cut out in the ground plane of the printed circuit board. As shown in Figure 34, the capacitors on ISENSE, VINS, VCOMP, and VSENSE must all be returned directly to the quiet portion of the ground plane, indicated by Signal GND, and not the high current return path of the converter, shown as the Power GND. Because the example circuit in Figure 34 uses surface mount components, the ICOMP capacitor, C10, has its own dedicated return to the GND pin.

Table 2. Layout Components

REFERENCE DESIGNATOR FUNCTION
U1 UCC28019A
Q1 Main switch
R1 RGATE
R5 Pull-down resistor on GATE
C13, C14 VCC bypass capacitors
C10 ICOMP compensation, CICOMP
R6 Inrush current limiting resistor, RISENSE
C11 ISENSE filter, CISENSE
R12, R13, R14 RFB1 on VSENSE
R18 RFB2 on VSENSE
C16 CVSENSE
R16, C17, C15 VCOMP compensation components, RVCOMP, CVCOMP, CVCOMP_P
C12, R17 CVINS, RVINS2 on VINS
D2 Boost diode

10.2 Layout Example

UCC28019A layout_lus828.gif Figure 34. Recommended Layout for the UCC28019A