Table 2. UCC27201A-Q1 Design Requirements

8.2.2.1 Switching the MOSFETs

Achieving optimum drive performance at high frequency efficiently requires special attention to layout and minimizing parasitic inductances. Care must be taken at the driver die and package level as well as the PCB layout to reduce parasitic inductances as much as possible. Figure 18 shows the main parasitic inductance elements and current flow paths during the turn ON and OFF of the MOSFET by charging and discharging its CGS capacitance.

Figure 18. MOSFET Drive Paths and Circuit Parasitics

The I_SOURCE current charges the C_GS gate capacitor and the I_SINK current discharges it. The rise and fall time of the voltage across the gate to source defines how quickly the MOSFET can be switched. Based on actual measurements, the analytical curves in Figure 19 and Figure 20 indicate the output voltage and current of the drivers during the discharge of the load capacitor. Figure 19 shows voltage and current as a function of time. Figure 20 indicates the relationship of voltage and current during fast switching. These figures demonstrate the actual switching process and limitations due to parasitic inductances.

Figure 19. Turn-Off Voltage and Current vs Time

Figure 20. Turn-Off Voltage and Current Switching Diagram

Turning off the MOSFET needs to be achieved as fast as possible to minimize switching losses. For this reason, the UCC27201A-Q1 driver is designed for high peak currents and low output resistance. The sink capability is specified as 0.18 V at 100-mA dc current implying 1.8-Ω R_DS(on). With 12-V drive voltage, no parasitic inductance and a linear resistance, one would expect initial sink current amplitude of 6.7 A for both high-side and low-side drivers. Assuming a pure R-C discharge circuit of the gate capacitor, one would expect the voltage and current waveforms to be exponential. Due to the parasitic inductances and non-linear resistance of the driver MOSFET’S, the actual waveforms have some ringing and the peak-sink current of the drivers is approximately 3.3 A as shown in Figure 14. The overall parasitic inductance of the drive circuit is estimated at 4 nH. The internal parasitic inductance of the SOIC-8 package is estimated to be 2 nH including bond wires and leads.

Actual measured waveforms are shown in Figure 21 and Figure 22. As shown, the typical rise time of 8 ns and fall time of 7 ns is conservatively rated.

Figure 21. V_LO and V_HO Rise Time, 1-nF Load, 5 ns/Div

Figure 22. V_LO and V_HO Fall Time, 1-nF Load, 5-ns/Div

8.2.2.2 Dynamic Switching of the MOSFETs

The true behavior of MOSFETS presents a dynamic capacitive load primarily at the gate to source threshold voltage. Using the turn off case as the example, when the gate to source threshold voltage is reached the drain voltage starts rising, the drain to gate parasitic capacitance couples charge into the gate resulting in the turn off plateau. The relatively low threshold voltages of many MOSFETS and the increased charge that has to be removed (Miller charge) makes good driver performance necessary for efficient switching. An open loop half bridge power converter was utilized to evaluate performance in actual applications. The schematic of the half-bridge converter is shown in Figure 17. The turn off waveforms of the UCC27201A-Q1 driving two MOSFETs in parallel is shown in Figure 23 and Figure 24.

Figure 23. V_LO Fall Time in Half-Bridge Converter

Figure 24. V_HO Fall Time in Half-Bridge Converter

8.2.2.3 Delay Matching and Narrow Pulse Widths

The total delays encountered in the PWM, driver and power stage need to be considered for a number of reasons, primarily delay in current limit response. Also to be considered are differences in delays between the drivers which can lead to various concerns depending on the topology. The sync-buck topology switching requires careful selection of dead-time between the high- and low-side switches to avoid 1) cross conduction and 2) excessive body diode conduction. Bridge topologies can be affected by a resulting volt-sec imbalance on the transformer if there is imbalance in the high and low side pulse widths in a steady state condition.

Narrow pulse width performance is an important consideration when transient and short circuit conditions are encountered. Although there may be relatively long steady state PWM output-driver-MOSFET signals, very narrow pulses may be encountered in 1) soft start, 2) large load transients, and 3) short circuit conditions.

The UCC27201A-Q1 driver offers excellent performance regarding high and low-side driver delay matching and narrow pulse width performance. The delay matching waveforms are shown in Figure 25 and Figure 26. The UCC27201A-Q1 driver narrow pulse performance is shown in Figure 27 and Figure 28.

Figure 25. V_LO and V_HO Rising Edge Delay Matching

Figure 27. 20-ns Input Pulse Delay Matching

Figure 26. V_LO and V_HO Falling Edge Delay Matching

Figure 28. 10-ns Input Pulse Delay Matching

8.2.2.4 Boot Diode Performance

The UCC27201A-Q1 driver incorporates the bootstrap diode necessary to generate the high side bias internally. The characteristics of this diode are important to achieve efficient, reliable operation. The dc characteristics to consider are V_F and dynamic resistance. A low V_F and high dynamic resistance results in a high forward voltage during charging of the bootstrap capacitor. The UCC27201A-Q1 has a boot diode rated at 0.65-V V_F and dynamic resistance of 0.6 Ω for reliable charge transfer to the bootstrap capacitor. The dynamic characteristics to consider are diode recovery time and stored charge. Diode recovery times that are specified with no conditions can be misleading. Diode recovery times at no forward current (I_F) can be noticeably less than with forward current applied. The UCC27201A-Q1 boot diode recovery is specified at 20 ns at I_F = 20 mA, I_REV = 0.5 A. At 0 mA I_F, the reverse recovery time is 15 ns.

Another less obvious consideration is how the stored charge of the diode is affected by applied voltage. On every switching transition when the HS node transitions from low to high, charge is removed from the boot capacitor to charge the capacitance of the reverse biased diode. This is a portion of the driver power losses and reduces the voltage on the HB capacitor. At higher applied voltages, the stored charge of the UCC27201A-Q1 PN diode is often less than a comparable Schottky diode.