ZHCSPG3A May   2008  – July 2022 UC2843A-Q1

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Electrical Characteristics
    5. 6.5 Thermal Information
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Pulse-by-Pulse Current Limiting
      2. 7.3.2 Current Sense Circuit
      3. 7.3.3 Error Amplifier Configuration
      4. 7.3.4 Undervoltage Lockout
      5. 7.3.5 Oscillator
    4. 7.4 Device Functional Modes
      1. 7.4.1 Normal Operation
      2. 7.4.2 Undervoltage Lockout (UVLO) Start-Up
      3. 7.4.3 UVLO Turnoff Mode
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
        1. 11.1.1.1 Custom Design With WEBENCH® Tools
      2. 11.1.2 Device Nomenclature
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Related Links
    4. 11.4 接收文档更新通知
    5. 11.5 支持资源
    6. 11.6 Trademarks
    7. 11.7 Electrostatic Discharge Caution
    8. 11.8 术语表
  12. 12Mechanical, Packaging, and Orderable Information

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7.3.5 Oscillator

GUID-24360D9E-F0BD-4649-A5E6-4D8C3B357B63-low.gifFigure 7-4 Oscillator Frequency vs Timing Resistance
GUID-70AF8685-C063-475D-9A1A-99D7DC861191-low.gifFigure 7-5 Maximum Duty Cycle vs Timing Resistance
GUID-FB69F797-B4DB-4514-A5A2-9A3DA3E77754-low.gifFigure 7-6 Oscillator Section
GUID-6E8B536D-DDFC-42A2-9CA3-6E30ADBF91D9-low.gifFigure 7-7 Slope Compensation

Precision operation at high frequencies with an accurate maximum duty cycle, see Figure 7-5, can now be obtained with the UC2843A-Q1 device due to its trimmed oscillator discharge current. This nullifies the effects of production variations in the initial discharge current or dead time.

A fraction of the oscillator ramp can be resistively summed with the current sense signal, to provide slope compensation for converters requiring duty cycles over 50%. Capacitor C forms a filter with R2 to suppress the leading-edge switch spikes.