ZHCSD29A November   2014  – November 2014 TVB1440

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 简化电路原理图
  5. 5 修订历史记录
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 Handling Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Switching Characteristics
    8. 7.8 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Equalization
      2. 8.3.2 Configurable Output
      3. 8.3.3 Squelch
    4. 8.4 Device Functional Modes
      1. 8.4.1 Active Mode
      2. 8.4.2 Shutdown Mode
      3. 8.4.3 Squelch Mode
    5. 8.5 Programming
      1. 8.5.1 Local I2C Interface
      2. 8.5.2 Receiver (IN[3:0]P/N) Adjustments
        1. 8.5.2.1 Equalization Level
        2. 8.5.2.2 Squelch Level
      3. 8.5.3 Main Link Output [OUT[3:0]P/N] Adjustments
        1. 8.5.3.1 LINK Address Space
      4. 8.5.4 Example Script
    6. 8.6 Register Maps
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Typical Application
        1. 9.1.1.1 Design Requirements
        2. 9.1.1.2 Detailed Design Procedure
          1. 9.1.1.2.1 Common 4k2k TV Panel Configuration
          2. 9.1.1.2.2 1Max Stream Rate
          3. 9.1.1.2.3 Encoded Stream Rate
          4. 9.1.1.2.4 TVB1440 Configuration
          5. 9.1.1.2.5 Receiver Equalization Setting
          6. 9.1.1.2.6 Transmitter Settings
          7. 9.1.1.2.7 RESET
  10. 10Power Supply Recommendations
    1. 10.1 Power-Up Sequence
    2. 10.2 Power-Down Sequence
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Differential Pairs
      2. 11.1.2 Layout Example
      3. 11.1.3 Placement
      4. 11.1.4 Package Specific
      5. 11.1.5 Ground
  12. 12器件和文档支持
    1. 12.1 商标
    2. 12.2 静电放电警告
    3. 12.3 Export Control Notice
    4. 12.4 术语表
  13. 13机械封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

6 Pin Configuration and Functions

VQFN 0.5 mm Pitch
RGZ 48 Pin
Top View
po_slase51.gif

Pin Functions

PIN DESCRIPTION
SIGNAL NO. I/O
DATA LANES PINS
IN0p, IN0n 38, 39 Input
(100Ω diff)		 Lane 0 Differential Input
IN1p, IN1n 41, 42 Lane 1 Differential Input
IN2p, IN2n 44, 45 Lane 2 Differential Input
IN3p, IN3n 47, 48 Lane 3 Differential Input
OUT0p, OUT0n 23, 22 Output
(100Ω diff)		 Lane 0 Differential Output
OUT1p, OUT1n 20, 19 Lane 1 Differential Output
OUT2p, OUT2n 17, 16 Lane 2 Differential Output
OUT3p, OUT3n 14, 13 Lane 3 Differential Output
CONTROL PINS
ADDR 3 3-level Input I2C Target Address Select.
EN 26 I Device Enable. This input incorporates internal pullup of 200 kΩ.
NC 7, 40, 46 No Connect. These terminals may be left un-connected, or connect to GND.
RSTN 35 I Active Low Device Reset. This is 1.1V input. This input includes a 150kΩ resistor to the VDDD core supply. An external capacitor to GND is recommended on the RSTN input to provide a power-up delay. This signal is used to place the TVB1440 into Shutdown mode for the lowest power consumption. When the RSTN input is asserted, all outputs are high-impedance, and inputs are ignored; all I2C registers are reset to their default values. At power up, the RSTN input must not be de-asserted until the VCC and VDD supplies have reached at least the minimum recommended supply voltage level.
RSVD1 10 I Reserved pins. Please connect the pin to GND through 1K resistor.
RSVD2 11 I Reserved pins. Please connect the pin to VCC through 1K resistor.
RSVD3 27 I Reserved pins. Please connect the pin to VCC through 1K resistor.
RSVD4 28 I Reserved pins. Please connect the pin to GND through 1K resistor.
SCL_CTL
SDA_CTL		 4
5		 I/O Bidirectional I2C interface to configure TVB1440. This interface is active independent of EN input but inactive when RSTN is low.
TEST1-6 8, 9, 29, 30, 33, 34 Test Outputs. Do not connect.
SUPPLY AND GROUND PINS
GND 18, 24, 31, PAD Ground. Reference GND connections include the device package exposed thermal pad.
VDD 2, 6, 12, 15, 21, 25, 32, 37, 43 Low voltage supply for analog and digital core. Nominally 1.1V
VCC 1, 36 3.3V Supply