SLLSFB2A April   2020  – June 2026 TUSB1146

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4  TUSB1146 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Power Supply Characteristics
    6. 5.6  Control I/O DC Electrical Characteristics
    7. 5.7  USB and DP Electrical Characteristics
    8. 5.8  DCI Electrical Characteristics
    9. 5.9  Timing Requirements
    10. 5.10 Switching Characteristics
    11. 5.11 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 USB 3.1
      2. 7.3.2 DisplayPort
      3. 7.3.3 4-level Inputs
      4. 7.3.4 Receiver Linear Equalization
    4. 7.4 Device Functional Modes
      1. 7.4.1 Device Configuration in GPIO Mode
      2. 7.4.2 Device Configuration In I2C Mode
      3. 7.4.3 DisplayPort Mode
      4. 7.4.4 Linear EQ Configuration
      5. 7.4.5 VOD modes
        1. 7.4.5.1 Linearity VOD
        2. 7.4.5.2 Limited VOD
      6. 7.4.6 Transmit Equalization
      7. 7.4.7 USB3.1 Modes
      8. 7.4.8 Downstream Facing Port Adaptive Equalization
        1. 7.4.8.1 Fast Adaptive Equalization in I2C Mode
        2. 7.4.8.2 Full Adaptive Equalization
    5. 7.5 Programming
      1. 7.5.1 Transition between Modes
      2. 7.5.2 Pseudocode Examples
        1. 7.5.2.1 Fast AEQ with linear redriver mode
        2. 7.5.2.2 Fast AEQ with limited redriver mode
        3. 7.5.2.3 Full AEQ with linear redriver mode
        4. 7.5.2.4 Full AEQ with limited redriver mode
      3. 7.5.3 TUSB1146 I2C Address Options
      4. 7.5.4 TUSB1146 I2C Slave Behavior
  9. 8 Registers
    1. 8.1 Register Maps
      1. 8.1.1 TUSB1146 Registers
        1. 8.1.1.1  General_1 Register (Offset = 0xA) [reset = 0x1]
        2. 8.1.1.2  DCI_TXEQ_CTRL Register (Offset = 0xB) [reset = 0x6C]
        3. 8.1.1.3  DP01EQ_SEL Register (Offset = 0x10) [reset = 0x0]
        4. 8.1.1.4  DP23EQ_SEL Register (Offset = 0x11) [reset = 0x0]
        5. 8.1.1.5  DisplayPort_1 Register (Offset = 0x12) [reset = 0x0]
        6. 8.1.1.6  DisplayPort_2 Register (Offset = 0x13) [reset = 0x0]
        7. 8.1.1.7  AEQ_CONTROL1 Register (Offset = 0x1C) [reset = 0xF0]
        8. 8.1.1.8  AEQ_CONTROL2 Register (Offset = 0x1D) [reset = 0x20]
        9. 8.1.1.9  AEQ_LONG Register (Offset = 0x1E) [reset = 0x77]
        10. 8.1.1.10 USBC_EQ Register (Offset = 0x20) [reset = 0x0]
        11. 8.1.1.11 SS_EQ Register (Offset = 0x21) [reset = 0x0]
        12. 8.1.1.12 USB3_MISC Register (Offset = 0x22) [reset = 0x44]
        13. 8.1.1.13 USB_STATUS Register (Offset = 0x24) [reset = 0x41]
        14. 8.1.1.14 VOD_CTRL Register (Offset = 0x32) [reset = 0x40]
        15. 8.1.1.15 AEQ_STATUS Register (Offset = 0x3B) [reset = 0x0]
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 USB and DP Upstream Facing Port (USB Host / DP GPU to USB-C receptacle) Configuration
        2. 9.2.2.2 USB Downstream Facing Port (USB-C receptacle to USB Host) Configuration
          1. 9.2.2.2.1 Fixed Equalization
          2. 9.2.2.2.2 Fast Adaptive Equalization
          3. 9.2.2.2.3 Full Adaptive Equalization
      3. 9.2.3 Application Curve
    3. 9.3 System Examples
      1. 9.3.1 USB 3.1 Only
      2. 9.3.2 USB 3.1 and 2 Lanes of DisplayPort
      3. 9.3.3 DisplayPort Only
  11. 10Power Supply Recommendations
  12. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  13. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 Support Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  14. 13Revision History
  15. 14Mechanical, Packaging, and Orderable Information

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5.7 USB and DP Electrical Characteristics

over operating free-air temperature and voltage range (unless otherwise noted)
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
USB Gen 2 Differential Receiver (RX1p/n, RX2p/n, SSTXp/n)
V(RX-DIFF-PP)Input differential peak-peak voltage swing linear dynamic rangeAC-coupled differential peak-to-peak signal measured post CTLE through a reference channel1200mVpp
V(RX-DC-CM)Common-mode voltage bias in the receiver (DC)0V
VRX_CM-INSTMax Instantaneous RX DC common mode voltage change under all operating conditions (OFF to ON, Disabled to USB, etc…)Measured at non-TUSB1146 side of AC coupling capacitor with  200-kΩ load.-200 500mV
R(RX-DIFF-DC)Differential input impedance (DC)Present after a GEN2 device is detected on TXP/TXN7290120Ω
R(RX-CM-DC)Receiver DC common mode impedancePresent after a GEN2 device is detected on TXP/TXN1830Ω
Z(RX-HIGH-IMP-DC-POS)Common-mode input impedance with termination disabled (DC)Present when no GEN2 device is detected on TXP/TXN. Measured over the range of 0-500mV with respect to GND.25kΩ
V(SIGNAL-DET-DIFF-PP)Input differential peak-to-peak signal detect assert levelAt 10 Gbps, no input loss, PRBS7 pattern80mV
V(RX-IDLE-DET-DIFF-PP)Input differential peak-to-peak signal detect de-assert LevelAt 10 Gbps, no input loss, PRBS7 pattern60mV
V(RX-LFPS-DET-DIFF-PP)Low frequency periodic signaling (LFPS) detect thresholdBelow the minimum is squelched100300mV
V(RX-CM-AC-P)Peak RX AC common-mode voltageMeasured at package pin150mV
C(RX)RX input capacitance to GNDAt 5 GHz; 0.881pF
RL(RX-DIFF)Differential return Loss50 MHz – 1.25 GHz at 90 Ω; –19dB
5 GHz at 90 Ω; –10dB
RL(RX-CM)Common-mode return loss50 MHz – 5 GHz at 90 Ω; –10dB
EQ_SSTX15SSTX Receiver equalization at 5 GHzFLIPSEL = 0; SSEQ_SEL = 15;11.5dB
EQ_RX15RX1 Receiver equalization at 5 GHzFLIPSEL = 0; EQ1_SEL = 15;11.0dB
CAC-USB1Required external AC capacitor on SSTX75265nF
CAC-USB2Optional external AC capacitor on RX1 and RX2.297363nF
USB Gen 2 Differential Transmitter (TX1p/n, TX2p/n, SSRXp/n)
VTX(DIFF-PP)Transmitter dynamic differential voltage swing range.1200mVpp
VTX(RCV-DETECT)Amount of voltage change allowed during receiver detection600mV
VTX-CM-INST-ONOFFMax Instantaneous TX DC common mode voltage change under operating condition:  OFF to ON, ON to OFF, during Rx.Detect; Disconnect to U0, U2/U3 to U0.Measured single-ended at non-TUSB1146 side of AC coupling capacitor with  200-kΩ load.-500 800mV
VTX(CM-IDLE-DELTA)Transmitter idle common-mode voltage change while in U2/U3 and not actively transmitting LFPS–300600mV
VTX(DC-CM)Common-mode voltage bias in the transmitter (DC)01V
VTX(CM-AC-PP-ACTIVE)Tx AC common-mode voltage activeMax mismatch from Txp + Txn for both time and amplitude100mVpp
VTX(IDLE-DIFF-AC-PP)AC electrical idle differential peak-to-peak output voltageAt package pins010mV
VTX(CM-DC-ACTIVE-IDLE-DELTA)Absolute DC common-mode voltage between U1 and U0At package pin200mV
RTX(DIFF)Differential impedance of the driver8090120Ω
RTX(CM)Common-mode impedance of the driverMeasured with respect to AC ground over
0–500 mV		1830Ω
VSSRX-LIMITED-VODL0SSRX differential peak-to-peak voltage when configured for limited redriver and LINR_L0TX_PRESHOOT_EN = 0; TX_DEEMPHASIS_EN = 0;800mVpp
VSSRX-LIMITED-VODL1SSRX differential peak-to-peak voltage when configured for limited redriver and LINR_L1TX_PRESHOOT_EN = 0; TX_DEEMPHASIS_EN = 0;900mVpp
VSSRX-LIMITED-VODL2SSRX differential peak-to-peak voltage when configured for limited redriver and LINR_L2TX_PRESHOOT_EN = 0; TX_DEEMPHASIS_EN = 0;1000mVpp
VSSRX-LIMITED-VODL3SSRX differential peak-to-peak voltage when configured for limited redriver and LINR_L3TX_PRESHOOT_EN = 0; TX_DEEMPHASIS_EN = 0;1100mVpp
VSSRX-DE-RATIO0SSRX de-emphasis when configured for limited redriver and de-emphasis enabled.TX_PRESHOOT_EN = 0; TX_DEEMPHASIS_EN = 1; TX_DEEPHASIS = 2'b00; USB_SSRX_VOD = 2'b00 (LINR_L3); Refer to Figure 6-9-1.5dB
VSSRX-DE-RATIO1SSRX de-emphasis when configured for limited redriver and de-emphasis enabled.TX_PRESHOOT_EN = 0; TX_DEEMPHASIS_EN = 1; TX_DEEPHASIS = 2'b01;  USB_SSRX_VOD = 2'b00 (LINR_L3); Refer to Figure 6-9-2.1dB
VSSRX-DE-RATIO2SSRX de-emphasis when configured for limited redriver and de-emphasis enabled.TX_PRESHOOT_EN = 0; TX_DEEMPHASIS_EN = 1; TX_DEEPHASIS = 2'b10;  USB_SSRX_VOD = 2'b00 (LINR_L3); Refer to Figure 6-9-3.2dB
VSSRX-DE-RATIO3SSRX de-emphasis when configured for limited redriver and de-emphasis enabled.TX_PRESHOOT_EN = 0; TX_DEEMPHASIS_EN = 1; TX_DEEPHASIS = 2'b11;  USB_SSRX_VOD = 2'b00 (LINR_L3); Refer to Figure 6-9-3.8dB
VSSRX-PRESH-RATIO0SSRX pre-shoot level when configured for limited redriver and pre-shoot enabled.TX_PRESHOOT_EN = 1; TX_DEEMPHASIS_EN = 0; TX_PRESHOOT = 2'b00;  USB_SSRX_VOD = 2'b00 (LINR_L3); Refer to Figure 6-101.5dB
VSSRX-PRESH-RATIO1SSRX pre-shoot level when configured for limited redriver and pre-shoot enabled.TX_PRESHOOT_EN = 1; TX_DEEMPHASIS_EN = 0; TX_PRESHOOT = 2'b01;  USB_SSRX_VOD = 2'b00 (LINR_L3);  Refer to Figure 6-102.0dB
VSSRX-PRESH-RATIO2SSRX pre-shoot level when configured for limited redriver and pre-shoot enabled.TX_PRESHOOT_EN = 1; TX_DEEMPHASIS_EN = 0; TX_PRESHOOT = 2'b10;  USB_SSRX_VOD = 2'b00 (LINR_L3);  Refer to Figure 6-102.3dB
VSSRX-PRESH-RATIO3SSRX pre-shoot level when configured for limited redriver and pre-shoot enabled.TX_PRESHOOT_EN = 1; TX_DEEMPHASIS_EN = 0; TX_PRESHOOT = 2'b11;  USB_SSRX_VOD = 2'b00 (LINR_L3);  Refer to Figure 6-102.8dB
ITX(SHORT)TX short circuit currentTX± shorted to GND40mA
CTX(PARASITIC)TX input capacitance for return lossAt package pins, at 5 GHz0.91.25pF
RLTX(DIFF)Differential return loss50 MHz – 1.25 GHz at 90 Ω-30dB
5 GHz at 90 Ω-21dB
RLTX(CM)Common-mode return loss50 MHz – 5 GHz at 90 Ω-10dB
CTX-AC(COUPLING)External required AC coupling capacitor75265nF
AC Characteristics
CrosstalkDifferential crosstalk between TX and RX signal pairsat 5 GHz; EQ = 0;–30dB
CPLF-LINRL0Low-frequency 1-dB compression point at LINR_L0 setting.  At 100 MHz, 200 mVpp < VID < 1200 mVpp600mVpp
CPHF-LINRL0High-frequency 1-dB compression point at LINR_L0 setting.   At 5 GHz, 200 mVpp < VID < 1200 mVpp550mVpp
CPLF-LINRL1Low-frequency 1-dB compression point at LINR_L1 setting.   At 100 MHz, 200 mVpp < VID < 1200 mVpp700mVpp
CPHF-LINRL1High-frequency 1-dB compression point at LINR_L1 setting.   At 5 GHz, 200 mVpp < VID < 1200 mVpp650mVpp
CPLF-LINRL2Low-frequency 1-dB compression point at LINR_L2 setting.   At 100 MHz, 200 mVpp < VID < 1200 mVpp800mVpp
CPHF-LINRL2High-frequency 1-dB compression point at LINR_L2 setting.   At 5 GHz, 200 mVpp < VID < 1200 mVpp750mVpp
CPLF-LINRL3Low-frequency 1-dB compression point at LINR_L3 setting.   At 100 MHz, 200 mVpp < VID < 1200 mVpp900mVpp
CPHF-LINRL3High-frequency 1-dB compression point at LINR_L3 setting.   At 5 GHz, 200 mVpp < VID < 1200 mVpp830mVpp
fLFLow frequency cutoff200 mVPP< VID < 1200 mVPP2050kHz
tTX_DJ_USBTX output deterministic residual jitter when operating in USB mode.Optimual EQ setting; 12-in prechannel (SDD21 = -11.2dB); 1.6-in post channel (SDD21 = -1.8dB); PRBS7; 10 Gbps.07UI
tTX_DJ_DPTX output deterministic residual jitter when operating in DP mode.Optimual EQ setting;12-in prechannel (SDD21 = -11.2dB); 1.6-in post channel (SDD21 = -1.8dB); PRBS7; 8.1 Gbps.04UI
DisplayPort Receiver (DP[3:0]p/n)
VID(PP)Peak-to-peak input differential dynamic voltage range1400V
VICInput common mode voltage01.752V
VRX_CM-INSTMax Instantaneous RX DC common mode voltage change under all operating conditions (OFF to ON, Disabled to 4DP, etc…)Measured single-ended at non-TUSB1146 side of AC coupling capacitor with  50-Ω load.-300500mV
dRData rate10Gbps
R(ti)Input termination resistance7590110Ω
C(AC)External required AC coupling capacitance75265nF
EQ_DP15DP0 Receiver equalization at 4.05 GHzFLIPSEL = 0; DP0EQ_SEL = 15;12dB
EQ_DP15DP0 Receiver equalization at 5 GHzFLIPSEL = 0; DP0EQ_SEL = 15;12.3dB
DisplayPort Transmitter (TX1p/n, TX2p/n, RX1p/n, RX2p/n)
VTX-CM-INSTMax Instantaneous TX DC common mode voltage change under all operating conditions (Disabled to 4DP, etc…)Measured at non-TUSB1146 side of AC coupling capacitor with  50-Ω load.-500 1000mV
VTX(DC-CM)Common-mode voltage bias in the transmitter (DC)01V
AUXp or AUXn and SBU1 or SBU2
RONOutput ON resistanceVCC = 3.3 V; VI = 0 to 0.4 V for AUXp;
VI = 2.7 V to 3.6 V for AUXn		25.510Ω
ΔRONON resistance mismatch within pairVCC = 3.3 V; VI = 0 to 0.4 V for AUXP;
VI = 2.7 V to 3.6 V for AUXN		2.5Ω
RON(FLAT)ON resistance flatness (RON max – RON min) measured at identical VCC and temperatureVCC = 3.3 V; VI = 0 to 0.4 V for AUXp;
VI = 2.7 V to 3.6 V for AUXn		2Ω
V(AUXP_DC_CM)AUX Channel DC common mode voltage for AUXp and SBU1.VCC = 3.3 V;00.4V
V(AUXN_DC_CM)AUX Channel DC common mode voltage for AUXn and SBU2VCC = 3.3 V;2.73.6V
C(AUX_ON)ON-state capacitanceVCC = 3.3 V; CTL1 = 1; VI = 0 V
or 3.3 V		47pF
C(AUX_OFF)OFF-state capacitanceVCC = 3.3 V; CTL1 = 0; VI = 0 V
or 3.3 V		36pF