ZHCSHW9B March   2018  – October 2023 TUSB1002A

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 4-Level Control Inputs
      2. 7.3.2 Linear Equalization
      3. 7.3.3 Adjustable VOD Linear Range and DC Gain
      4. 7.3.4 USB3.2 Dual Channel Operation (MODE = “F”)
      5. 7.3.5 USB3.2 Single Channel Operation (MODE = “1”)
      6. 7.3.6 PCIe/SATA/SATA Express Redriver Operation (MODE = “R”; CFG1 = "0"; CFG2 = "0" )
      7. 7.3.7 Basic Redriver Operation (MODE = “0”)
    4. 7.4 Device Functional Modes
      1. 7.4.1 Shutdown Mode
      2. 7.4.2 Disconnect Mode
    5. 7.5 U0 Mode
    6. 7.6 U1 Mode
    7. 7.7 U2/U3 Mode
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical USB3.2 Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 ESD Protection
      4. 8.2.4 Application Curves
    3. 8.3 Typical SATA, PCIe and SATA Express Application
      1. 8.3.1 Design Requirements
      2. 8.3.2 Detailed Design Procedure
      3. 8.3.3 Application Curves
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 接收文档更新通知
    2. 9.2 支持资源
    3. 9.3 Trademarks
    4. 9.4 静电放电警告
    5. 9.5 术语表
  11. 10Mechanical, Packaging, and Orderable Information

封装选项

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机械数据 (封装 | 引脚)
  • RGE|24
散热焊盘机械数据 (封装 | 引脚)
订购信息

6.7 Switching Characteristics

over operating free-air temperature and voltage range (unless otherwise noted)
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
tIDLEEntryDelay from U0 to electrical idleVCC = 3.0 V; EN = 1; See Figure 6-1150ps
tIDLEEntry_U1U1 exit time. Break in electrical idle to transmission of LFPS.VCC = 3.0 V; EN = 1; See Figure 6-1150ps
tIDLEEntry_U2U3U2/U3 exit time; Break in electrical idle to transmission of LFPSVCC = 3.0 V; EN = 1; See Figure 6-16µs
tDIFF_DLYDifferential propagation delayVCC = 3.0 V; EN = 1;150ps
tPWRUP_ACTIVETime from assertion of EN to device active and performing Rx.Detect on both portsVCC = 3.0 V; EN = 1;8ms
tTX_RISE_FALLTransmitter rise/fall timeVCC = 3.3 V; EN = 1; 10 Gbps; 20% to 80% of differential output; 1200 mVpp linear range setting; Fast Input rise/fall time;27ps
tRF_MISMATCHTransmitter rise/fall mismatchVCC = 3.3 V; EN = 1; 10 Gbps; 20% to 80% of differential output; 1200 mVpp linear range setting; 1000 mVpp VID.6ps
tTX_DJTransmitter residual deterministic jitterVCC = 3.3 V; EN = 1; 10 Gbps; 1200 mVpp linear range setting;  Input channel loss of 12 dB; Output channel loss of 1.5 dB; Optimized EQ;0.05UI
GUID-5BE50F09-4DCD-4312-BB83-1DFF3129D60A-low.gif Figure 6-1 Idle Entry and Exit Latency
GUID-F4CA130B-F29F-4AC6-BC02-3ADCB2E374BB-low.gif Figure 6-2 Power-Up Diagram