ZHCS363L August 2011 – March 2017 TRF7970A
PRODUCTION DATA.
Table 6-45 describes the Interrupt Mask register. Table 6-46 describes the Collision Position register.
Default: 0x3E at POR = H and EN = L. Collision bits reset automatically after read operation. | |||
Bit | Name | Function | Description |
B7 | Col9 | Bit position of collision MSB | Supports ISO/IEC 14443 A |
B6 | Col8 | Bit position of collision | |
B5 | En_irq_fifo | Interrupt enable for FIFO | Default = 1 |
B4 | En_irq_err1 | Interrupt enable for CRC | Default = 1 |
B3 | En_irq_err2 | Interrupt enable for Parity | Default = 1 |
B2 | En_irq_err3 | Interrupt enable for Framing error or EOF | Default = 1 |
B1 | En_irq_col | Interrupt enable for collision error | Default = 1 |
B0 | En_irq_noresp | Enables no-response interrupt | Default = 0 |
Function: Displays the bit position of collision or error | |||
Default: 0x00 at POR = H and EN = L. Automatically reset after read operation. | |||
Bit | Name | Function | Description |
B7 | Col7 | Bit position of collision MSB | ISO/IEC 14443 A mainly supported, in the other protocols this register shows the bit position of error. Frame, SOF, EOF, parity, or CRC error. |
B6 | Col6 | ||
B5 | Col5 | ||
B4 | Col4 | ||
B3 | Col3 | ||
B2 | Col2 | ||
B1 | Col1 | ||
B0 | Col0 | Bit position of collision LSB |