ZHCS363L 数据表 | 德州仪器 TI.com.cn

6.10.1.4 FIFO Operation

The FIFO is a 127-byte register at address 0x1F with byte storage locations 0 to 126. FIFO data is loaded in a cyclical manner and can be cleared by a reset command (0x0F) (see Figure 6-12 showing this direct command).

Associated with the FIFO are two counters and three FIFO status flags. The first counter is a 7-bit FIFO byte counter (bits B0 to B6 in register 0x1C) that tracks the number of bytes loaded into the FIFO. If the number of bytes in the FIFO is n, the register value is n (number of bytes in FIFO register). For example, if 8 bytes are in the FIFO, the FIFO counter (Register 0x1C) has the hexadecimal value of 0x08 (binary value of 00001000).

A second counter (12 bits wide) indicates the number of bytes being transmitted (registers 0x1D and 0x1E) in a data frame. An extension to the transmission-byte counter is a 4-bit broken-byte counter also provided in register 0x1E (bits B0 to B3). Together these counters make up the TX length value that determines when the reader generates the EOF byte.

During transmission, the FIFO is checked for an almost-empty condition, and during reception for an almost-full condition. The maximum number of bytes that can be loaded into the FIFO in a single sequence is 127 bytes.

NOTE

The number of bytes in a frame, transmitted or received, can be greater than 127 bytes.

During transmission, the MCU loads the TRF7970A FIFO (or during reception the MCU removes data from the FIFO), and the FIFO counter counts the number of bytes being loaded into the FIFO. Meanwhile, the byte counter keeps track of the number of bytes being transmitted. An interrupt request is generated if the number of bytes in the FIFO triggers the watermark levels, which are configured in the Adjustable FIFO IRQ Levels register (0x14). The default setting is for the interrupt to be triggered when receiving 124 bytes during RX or having 4 bytes remaining during TX. These watermark levels are used so that MCU can send new data or read the data as necessary. The MCU must also validate the number of data bytes to be sent, so as to not surpass the value defined in the TX Length Byte registers (0x1D and 0x1E). The MCU also signals the transmit logic when the last byte of data is sent or was removed from the FIFO during reception.

Figure 6-13 shows an example of checking the FIFO Status register using SPI with SS.

TRF7970A check_fifo_status_reg_spi_slos743.png

Figure 6-13 Example of Checking the FIFO Status Register Using SPI With SS

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6.10.1.4 FIFO Operation