ZHCSMP8B November   2020  – March 2021 TPSM5D1806

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics (VIN = 12 V)
    7. 6.7 Typical Characteristics (VIN = 5 V)
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Adjustable Output Voltage
      2. 7.3.2  Frequency Selection
        1. 7.3.2.1 Synchronization
        2. 7.3.2.2 Allowable Switching Frequency
      3. 7.3.3  Minimum and Maximum Input Voltage
      4. 7.3.4  Recommended Settings
      5. 7.3.5  Device Mode Configuration
        1. 7.3.5.1 MODE1 (Operating Mode and Phase Position)
        2. 7.3.5.2 MODE2 (Setting the Switching Frequency)
      6. 7.3.6  Input Capacitors
      7. 7.3.7  Minimum Required Output Capacitance
      8. 7.3.8  Ambient Temperature Versus Total Power Dissipation
      9. 7.3.9  Remote Sense
      10. 7.3.10 Enable (EN) and Under Voltage Lockout (UVLO)
      11. 7.3.11 Soft Start
      12. 7.3.12 Power Good
      13. 7.3.13 Safe Start-up into Pre-Biased Outputs
      14. 7.3.14 BP5
      15. 7.3.15 Overcurrent Protection
      16. 7.3.16 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Active Mode
      2. 7.4.2 Shutdown Mode
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application (Dual Outputs)
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Custom Design With WEBENCH® Tools
        2. 8.2.2.2 Output Voltage Setpoint
        3. 8.2.2.3 Input Capacitors
        4. 8.2.2.4 Output Capacitor Selection
      3. 8.2.3 Typical Application (Paralleled Outputs)
        1. 8.2.3.1 Design Requirements
        2. 8.2.3.2 Detailed Design Procedure
          1. 8.2.3.2.1 Output Voltage Setpoint
          2. 8.2.3.2.2 Input Capacitors
          3. 8.2.3.2.3 Output Capacitor Selection
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Examples
      1. 10.2.1 Package Specifications
      2. 10.2.2 EMI
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
        1. 11.1.1.1 Custom Design With WEBENCH® Tools
    2. 11.2 接收文档更新通知
    3. 11.3 支持资源
    4. 11.4 Trademarks
    5. 11.5 静电放电警告
    6. 11.6 术语表
  12. 12Mechanical, Packaging, and Orderable Information

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机械数据 (封装 | 引脚)
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订购信息

5 Pin Configuration and Functions

GUID-25AF0806-647A-41B9-A40C-E57B03E81827-low.gif Figure 5-1 51-Pin RDB QFN Package(Top View)
Table 5-1 Pin Functions
Pin Type(1) Description
Name No.
AGND 42, 43 G Analog ground for the internal analog control circuit. Connect to PGND at one single point, away from noisy circuitry.
BP5 44 O Output of the internal 5-V regulator. Bypass this pin with a minimum of 1.5 µF of effective capacitance to AGND. Can be used as a pullup voltage for PGOOD signals.
DNC 7, 8, 31, 32 - Do not connect. Do not connect these pins to AGND, PGND, to another DNC pin, or to any other voltage. These pins are connected to internal circuitry. Each pin must be soldered to an isolated pad.
EN1 1 I Channel 1 Enable input. Float or pull high to enable. Can also be used to externally adjust EN UVLO by connecting a resistor divider between VIN and AGND.
EN2/ISHARE 46 I/O Multi-function pin:
Dual output configuration: Channel 2 Enable input. Float or pull high to enable. Can also be used to externally adjust EN UVLO by connecting resistor divider between VIN and AGND.
Parallel output configuration: Current balance node of the internal regulators. Leave this pin open.
FB1 40 I Channel 1 feedback input. Connect to output voltage of channel 1 with a resistor divider.
FB2/VSHARE 45 I/O Multi-function pin:
Dual output configuration: Channel 2 Feedback input. Connect to output voltage of channel 2 with a resistor divider.
Parallel output configuration: The COMP voltage of the internal regulators. Leave this pin open.
MODE1 37 I Mode setting pin. Programs channel configuration as either dual or parallel outputs and programs channel interleaving using a resistor between MODE1 pin and AGND. A 10-kΩ resistor is required between the MODE1 pin and MODE2 pin.
MODE2 38 I Mode setting pin. Select from four pre-set switching frequencies using a resistor between MODE2 pin and AGND. A 10-kΩ resistor is required between MODE1 pin and MODE2 pin.
PGND 10, 11, 12, 27, 28, 29, 47, 48, 49, 50, 51 G Power ground of the device. This is the return current path for the power stage of the device. Connect these pins to the bypass capacitors associated with VIN and VOUT. Connect pads 47, 48, 49, 50, and 51 to the PCB ground planes using multiple vias for optimal thermal performance. All pins must be connected together externally with a copper plane or pour directly under the device.
PGOOD1 3 O Channel 1 Power Good indicator output. This pin is an open-drain output, which asserts low during any fault condition. When used, a pullup resistor to BP5 or other external supply is required. Leave this pin open if unused.
PGOOD2/CLKO 2 O Multi-function pin:
Dual output configuration: Channel 2 Power Good indicator output. This pin is an open-drain output, which asserts low during any fault condition. When used, a pullup resistor to BP5 or other external supply is required. Leave this pin open if unused.
Parallel output configuration: 180° clock output. Leave this pin open if unused.
RS– 41 G For parallel output applications, this pin functions as remote sense negative input to the differential amplifier. Connect this pin to the point of ground regulation using a kelvin trace. For dual output configurations, this pin must be tied to AGND.
SS 39 I External Soft Start when configured for parallel output operation. Place a capacitor from SS to AGND to set output voltage rise time. For independent dual channel configurations, leave this pin open.
SW1 30 O Channel 1 power stage switch node. Can be used to monitor the switch node.
SW2 9 O Channel 2 power stage switch node. Can be used to monitor the switch node.
SYNC 36 I Synchronizes to external clock, or the CLKO pin of another device.
VIN 4, 5, 6, 33, 34, 35 I Power conversion input pins. Pins 4, 5, and 6 are not internally connected to pins 33, 34, and 35. Connection must be made using the PCB VIN plane. Bypass VIN pins with ceramic capacitance to PGND, close to the device.
VOUT1 20, 21, 22, 23, 24, 25, 26 O Channel 1 output voltage. These pins are connected to the internal output inductor. Connect to the output load. Place external bypass capacitors between these pins and PGND.
VOUT2 13, 14, 15, 16, 17, 18, 19 O Channel 2 output voltage. These pins are connected to the internal output inductor. Connect to the output load. Place external bypass capacitors between these pins and PGND.
(1) G = Ground, I = Input, O = Output