ZHCSLS0B July 2022 – April 2024 TPS929240-Q1
PRODUCTION DATA
请参考 PDF 数据表获取器件具体的封装图。
Table 6-126 lists the memory-mapped registers for the CTRL registers. All register offset addresses not listed in Table 6-126 should be considered as reserved locations and the register contents should not be modified.
Control Register
Offset | Acronym | Register Name | Section |
---|---|---|---|
90h | ADCCH | ADC Channel Selection Setting | Go |
91h | CLR | Control Register for Clear | Go |
92h | DEBUG | Control Register for Debug | Go |
93h | LOCK | Control Register for Register Lock | Go |
94h | CLRREG | Control Register for Clear Register | Go |
95h | CTRL-R | Reserved Register | Go |
96h | CTRLGATE | Gate Register for MISC and LOCK | Go |
97h | EEP | Control Register for EEP Operation | Go |
98h | EEPGATE | Gate Register for EEP | Go |
Complex bit access types are encoded to fit into small table cells. Table 6-127 shows the codes that are used for access types in this section.
Access Type | Code | Description |
---|---|---|
Read Type | ||
R | R | Read |
Write Type | ||
W | W | Write |
Reset or Default Value | ||
-n | Value after reset or the default value |
ADCCH is shown in Figure 6-120 and described in Table 6-128.
Return to the Summary Table.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | ADCCHSEL | ||||||
R-0h | R/W-0h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-5 | RESERVED | R | 0h | Reserved |
4-0 | ADCCHSEL | R/W | 0h | Channel selection setting for ADC voltage measurement, write this register automatically initiates the ADC conversion |
CLR is shown in Figure 6-121 and described in Table 6-129.
Return to the Summary Table.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CLRFS | CLRFAULT | CLRPOR | ||||
R-0h | R/W-0h | R/W-0h | R/W-0h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-3 | RESERVED | R | 0h | Reserved |
2 | CLRFS | R/W | 0h | Write 1 to force device to exit fail-safe state to normal state, automatically returns to 0 |
1 | CLRFAULT | R/W | 0h | Write 1 to clear all fault flags, automatically returns to 0 |
0 | CLRPOR | R/W | 0h | Write 1 to clear POR fault flag, automatically returns to 0 |
DEBUG is shown in Figure 6-122 and described in Table 6-130.
Return to the Summary Table.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | FORCEFS | FPRCEERR | |||||
R-0h | R/W-0h | R/W-0h | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-2 | RESERVED | R | 0h | Reserved |
1 | FORCEFS | R/W | 0h | Write 1 to force device to fail-safe state, automatically returns to 0 |
0 | FPRCEERR | R/W | 0h | Write 1 to set FLAG_ERR to 1 and ERR output pulled down for 50µs in normal state, automatically returns to 0 |
LOCK is shown in Figure 6-123 and described in Table 6-131.
Return to the Summary Table.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | BRTLOCK | CONFLOCK | IOUTLOCK | ||||
R-0h | R/W-0h | R/W-1h | R/W-1h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-3 | RESERVED | R | 0h | Reserved |
2 | BRTLOCK | R/W | 0h | BRT register lock
0h = Write protection is disabled 1h = Write protection is enabled |
1 | CONFLOCK | R/W | 1h | CONF register lock
0h = Write protection is disabled 1h = Write protection is enabled |
0 | IOUTLOCK | R/W | 1h | IOUT register lock
0h = Write protection is disabled 1h = Write protection is enabled |
CLRREG is shown in Figure 6-124 and described in Table 6-132.
Return to the Summary Table.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SOFTRESET | EEPLOAD | REGDEFAULT | ||||
R-0h | R/W-0h | R/W-0h | R/W-0h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-3 | RESERVED | R | 0h | Reserved |
2 | SOFTRESET | R/W | 0h | Write 1 to reset all state machine and all registers, automatically returns to 0 |
1 | EEPLOAD | R/W | 0h | Write 1 to load EEP data to corresponding registers, automatically returns to 0 |
0 | REGDEFAULT | R/W | 0h | Write 1 to set all registers to default value, automatically returns to 0 |
CTRL-R is shown in Figure 6-125 and described in Table 6-133.
Return to the Summary Table.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | |||||||
R-0h | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | RESERVED | R | 0h | Reserved |
CTRLGATE is shown in Figure 6-126 and described in Table 6-134.
Return to the Summary Table.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CTRLGATE | |||||||
R/W-0h | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | CTRLGATE | R/W | 0h | Gate register for DEBUG, LOCK and CLRREG registers access, write 43h, 4Fh, 44h and 45h one-byte by one-byte |
EEP is shown in Figure 6-127 and described in Table 6-135.
Return to the Summary Table.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | EEPPROG | EEPMODE | |||||
R-0h | R/W-0h | R/W-0h | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-2 | RESERVED | R | 0h | Reserved |
1 | EEPPROG | R/W | 0h | EEPROM burning starts in EEPROM programming state only, automatically returns to 0 |
0 | EEPMODE | R/W | 0h | EEPROM programming state setting
0h = Disabled 1h = Enabled |
EEPGATE is shown in Figure 6-128 and described in Table 6-136.
Return to the Summary Table.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
EEPGATE | |||||||
R/W-0h | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | EEPGATE | R/W | 0h | Gate register for EEP registers access, write 00h, 04h, 02h, 09h, 02h and 09h one-byte by one-byte |