ZHCSP77A December   2021  – March 2022 TPS92624-Q1

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Power Supply (SUPPLY)
        1. 7.3.1.1 Power-On Reset (POR)
        2. 7.3.1.2 Suppply Current in Fault Mode
      2. 7.3.2  Enable and Shutdown
      3. 7.3.3  Constant-Current Output and Setting (INx)
      4. 7.3.4  Thermal Sharing Resistor (OUTx and RESx)
      5. 7.3.5  PWM Control (PWMx)
      6. 7.3.6  Supply Control
      7. 7.3.7  Diagnostics
        1. 7.3.7.1 LED Short-to-GND Detection
        2. 7.3.7.2 LED Open-Circuit Detection
        3. 7.3.7.3 LED Open-Circuit Detection Enable (DIAGEN)
        4. 7.3.7.4 Overtemperature Protection
        5. 7.3.7.5 Low Dropout Operation
      8. 7.3.8  FAULT Bus Output With One-Fails-All-Fail
      9. 7.3.9  FAULT Table
      10. 7.3.10 LED Fault Summary
      11. 7.3.11 IO Pins Inner Connection
    4. 7.4 Device Functional Modes
      1. 7.4.1 Undervoltage Lockout, V(SUPPLY) < V(POR_rising)
      2. 7.4.2 Normal Operation V(SUPPLY) ≥ 4.5 V
      3. 7.4.3 Low-Voltage Dropout Operation
      4. 7.4.4 Fault Mode
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 BCM Controlled Rear Lamp With One-Fails-All-Fail Setup
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Independent PWM Controlled Rear Lamp By MCU
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
        3. 8.2.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 接收文档更新通知
    2. 11.2 支持资源
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 术语表
  12. 12Mechanical, Packaging, and Orderable Information

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6.6 Timing Requirements

MIN NOM MAX UNIT
t(PWM_delay_rising) PWM rising edge delay, VIH(PWM) voltage to 10% of output current closed loop when V(SUPPLY) = 12 V, V(OUT) = 6 V, V(CS_REG) = 100 mV, R(SNSx) = 0.665 Ω and R(RESx) = 56 Ω, t1 as shown in Figure 7-1 3 6 µs
PWM rising edge delay, VIH(PWM) voltage to 10% of output current closed loop when V(SUPPLY) = 12 V, V(OUT) = 6 V, V(CS_REG) = 100 mV, R(SNSx) = 1 Ω and R(RESx) = 110 Ω, t1 as shown in Figure 7-1 3 6 µs
PWM rising edge delay, VIH(PWM) voltage to 10% of output current closed loop when V(SUPPLY) = 12 V, V(OUT) = 6 V, V(CS_REG) = 100 mV, R(SNSx) = 10 Ω and R(RESx) = 27 Ω, t1 as shown in Figure 7-1 3 6 µs
t(PWM_delay_falling) PWM falling edge delay, VIL(PWM) voltage to 90% of output current open loop when V(SUPPLY) = 12 V, V(OUT) = 6 V, V(CS_REG) = 100 mV, R(SNSx) = 0.665 Ω and R(RESx) = 56 Ω, t3 as shown in Figure 7-1 1.2 2.4 3.6 µs
PWM falling edge delay, VIL(PWM) voltage to 90% of output current open loop when V(SUPPLY) = 12 V, V(OUT) = 6 V, V(CS_REG) = 100 mV, R(SNSx) = 1 Ω and R(RESx) = 110 Ω, t3 as shown in Figure 7-1 1.6 2.6 4.2 µs
PWM falling edge delay, VIL(PWM) voltage to 90% of output current open loop when V(SUPPLY) = 12 V, V(OUT) = 6 V, V(CS_REG) = 100 mV, R(SNSx) = 10 Ω and R(RESx) = 27 Ω, t3 as shown in Figure 7-1 1.6 2.6 4.2 µs
t(Current_rising) Output current rising from 10% to 90% when V(SUPPLY) = 12 V, V(OUT) = 6 V, V(CS_REG) = 100 mV, R(SNSx) = 0.665 Ω and R(RESx) = 56 Ω, t2 as shown in Figure 7-1 2 5 µs
Output current rising from 10% to 90% when V(SUPPLY) = 12 V, V(OUT) = 6 V, V(CS_REG) = 100 mV, R(SNSx) = 1 Ω and R(RESx) = 110 Ω, t2 as shown in Figure 7-1 3 6 µs
Output current rising from 10% to 90% when V(SUPPLY) = 12 V, V(OUT) = 6 V, V(CS_REG) = 100 mV, R(SNSx) = 10 Ω and R(RESx) = 27 Ω, t2 as shown in Figure 7-1 3 6 µs
t(Current_falling) Output current falling from 90% to 10% when V(SUPPLY) = 12 V, V(OUT) = 6 V, V(CS_REG) = 100 mV, R(SNSx) = 0.665 Ω and R(RESx) = 56 Ω, t4 as shown in Figure 7-1 5 7 µs
Output current falling from 90% to 10% when V(SUPPLY) = 12 V, V(OUT) = 6 V, V(CS_REG) = 50 mV, R(SNSx) = 1 Ω and R(RESx) = 110 Ω, t4 as shown in Figure 7-1 1 2 µs
Output current falling from 90% to 10% when V(SUPPLY) = 12 V, V(OUT) = 6 V, V(CS_REG) = 50 mV, R(SNSx) = 10 Ω and R(RESx) = 27 Ω, t4 as shown in Figure 7-1 1 2 µs
t(STARTUP) SUPPLY rising edge to 10% output current when C(IREF) = C(ICTRL)= 10 pF, V(OUT) = 6 V, V(CS_REG) = 100 mV, R(SNSx) = 0.665 Ω and R(RESx) = 56 Ω, t5 as shown in Figure 7-1 55 100 µs
SUPPLY rising edge to 10% output current when C(IREF) = C(ICTRL)= 10 pF, V(OUT) = 6 V, V(CS_REG) = 100 mV, R(SNSx) = 10 Ω and R(RESx) = 110 Ω, t5 as shown in Figure 7-1 55 100 µs
SUPPLY rising edge to 10% output current when C(IREF) = C(ICTRL)= 10 pF, V(OUT) = 6 V, V(CS_REG) = 100 mV, R(SNSx) = 1 Ω and R(RESx) = 27 Ω, t5 as shown in Figure 7-1 55 100 µs
t(OPEN_deg) LED-open fault-deglitch time, t6 as shown in Figure 7-4 75 125 199 µs
t(SG_deg) Output short-to-ground detection deglitch time, t7 as shown in Figure 7-3 75 125 199 µs
t(Recover_deg) Open and Short fault recovery deglitch time, t8 as shown in Figure 7-4 and  Figure 7-3 75 125 199 µs
t(FAULT_deg) Fault pin digital deglitch time 7 10 13 µs
t(FAULT_recovery) Fault recovery delay time, t9 as shown in Figure 7-4 and Figure 7-3 30 50 84 µs
t(TSD_deg) Thermal over temperature deglitch time 30 50 84 µs