ZHCSL64D april   2019  – may 2023 TPS7H4001-SP

PRODMIX  

  1.   1
  2. 特性
  3. 应用
  4. 说明
  5. Revision History
  6. Device Options Table
  7. Pin Configuration and Functions
  8. Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics - All Devices
    6. 7.6  Electrical Characteristics: CDFP and KGD Options
    7. 7.7  Electrical Characteristics: HTSSOP (SHP) Option
    8. 7.8  Electrical Characteristics: HTSSOP (QMLP) Option
    9. 7.9  Quality Conformance Inspection
    10. 7.10 Typical Characteristics
  9. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  VIN and Power VIN Pins (VIN and PVIN)
      2. 8.3.2  Voltage Reference
      3. 8.3.3  Adjusting the Output Voltage
      4. 8.3.4  Safe Start-Up Into Prebiased Outputs
      5. 8.3.5  Error Amplifier
      6. 8.3.6  Enable and Adjust UVLO
      7. 8.3.7  Adjustable Switching Frequency and Synchronization (SYNC)
        1. 8.3.7.1 Internal Oscillator Mode
        2. 8.3.7.2 External Synchronization Mode
        3. 8.3.7.3 Primary-Secondary Operation Mode
      8. 8.3.8  Soft-Start (SS/TR)
      9. 8.3.9  Power Good (PWRGD)
      10. 8.3.10 Sequencing
      11. 8.3.11 Output Overvoltage Protection (OVP)
      12. 8.3.12 Overcurrent Protection
        1. 8.3.12.1 High-Side MOSFET Overcurrent Protection
        2. 8.3.12.2 Low-Side MOSFET Overcurrent Protection
      13. 8.3.13 Thermal Shutdown
      14. 8.3.14 Turn-On Behavior
      15. 8.3.15 Slope Compensation
        1. 8.3.15.1 Slope Compensation Requirements
      16. 8.3.16 Small Signal Model for Frequency Compensation
    4. 8.4 Device Functional Modes
      1. 8.4.1 Fixed-Frequency PWM Control
  10. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Operating Frequency
        2. 9.2.2.2 Output Inductor Selection
        3. 9.2.2.3 Output Capacitor Selection
        4. 9.2.2.4 Input Capacitor Selection
        5. 9.2.2.5 Soft-Start Capacitor Selection
        6. 9.2.2.6 Undervoltage Lockout (UVLO) Set Point
        7. 9.2.2.7 Output Voltage Feedback Resistor Selection
          1. 9.2.2.7.1 Minimum Output Voltage
        8. 9.2.2.8 Compensation Component Selection
      3. 9.2.3 Parallel Operation
      4. 9.2.4 Application Curve
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 接收文档更新通知
    3. 10.3 支持资源
    4. 10.4 Trademarks
    5. 10.5 静电放电警告
    6. 10.6 术语表
  12. 11Mechanical, Packaging, and Orderable Information

封装选项

请参考 PDF 数据表获取器件具体的封装图。

机械数据 (封装 | 引脚)
  • DDW|44
  • KGD|0
  • HKY|34
散热焊盘机械数据 (封装 | 引脚)
订购信息

Primary-Secondary Operation Mode

In primary-secondary mode, the RT pin of the primary device must be left floating. This sets the internal switching frequency of the device, fSW to a typical 500 kHz and the SYNC1 pin becomes an output clock at the same frequency and phase as fSW. In addition, the SYNC2 pin becomes an output clock at the same frequency but at 90° out of phase with respect to SYNC1. This SYNC1 and SYNC2 output clock signals, in combination with the state of the SYNC2 pins of the secondary devices, can be used to connect 2, 3, or 4 devices in parallel configuration. Figure 8-5 shows the SYNC1 and SYNC2 clock signals when the RT pin is floating in the primary device and how the signals can be used to generate the 90° out of phase clocks needed to connect 4 devices in parallel configuration (1 primary and 3 secondaries). The SYNC1b and SYNC2b indicate the clock signals being inverted either internally or due to the state of the SYNC2 pin in the secondary devices. When SYNC2 is connected to GND, the inverse functionality of the input clock signal in SYNC1 remains the same. When SYNC2 is connected to VIN, the input clock signal in SYNC1 does not get inverted. The RT pin of the secondary devices must have a resistor to GND corresponding to 500 kHz as indicated in Equation 4 and Figure 8-4. Low tolerance resistor values should be used for this purpose as this is necessary for proper slope compensation.

GUID-20201009-CA0I-LSJV-RMKN-Z3LM9KHXLQSQ-low.svg Figure 8-5 SYNC1 and SYNC2 Clock Signals in Primary-Secondary Mode

Figure 8-6 shows the SYNC1 and SYNC2 output signals from the primary device as well as signals and connections needed to operate 4 devices in parallel configuration. The fSW clock signal by each device represents the switching frequency signal for the respective device.

GUID-20201009-CA0I-SCDV-PJRQ-3BZRWTJN9HGL-low.svg Figure 8-6 Parallel Operation With SYNC1 and SYNC2 Pins

The 3 modes previously described are summarized in Table 8-1.

Table 8-1 Switching Frequency, SYNC, and RT Pin Usage Table
MODE RT PIN SYNC1 PIN SYNC2 PIN SWITCHING FREQUENCY
Internal oscillator Resistor to GND based on Figure 8-4 Floating GND Configurable using internal oscillator from 100 kHz to 1 MHz depending on RT resistor value
External synchronization External input clock. Signal will be inverted internally GND or VIN Internally synchronized to external clock between 100 kHz to 1 MHz
Primary Float Outputs 500-kHz clock in phase with internal switching frequency Outputs 500-kHz clock at 90° out of phase with internal switching frequency 500 kHz