ZHCSJO2C May   2019  – April 2020 TPS7B81-Q1

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
    1.     Device Images
      1.      典型应用原理图
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Device Enable (EN)
      2. 7.3.2 Undervoltage Shutdown
      3. 7.3.3 Current Limit
      4. 7.3.4 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Operation With VIN Lower Than 3 V
      2. 7.4.2 Operation With VIN Larger Than 3 V
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Power Dissipation
        1. 8.1.1.1 Estimating Junction Temperature
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Input Capacitor
        2. 8.2.2.2 Output Capacitor
      3. 8.2.3 Application Curve
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11器件和文档支持
    1. 11.1 接收文档更新通知
    2. 11.2 支持资源
    3. 11.3 商标
    4. 11.4 静电放电警告
    5. 11.5 Glossary
  12. 12机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

8.1.1 Power Dissipation

Circuit reliability demands that proper consideration is given to device power dissipation, location of the circuit on the printed circuit board (PCB), and correct sizing of the thermal plane. The PCB area around the regulator must be as free as possible of other heat-generating devices that cause added thermal stresses.

As a first-order approximation, power dissipation in the regulator depends on the input-to-output voltage difference and load conditions. PD can be approximated using Equation 1:

Equation 1. PD = (VIN – VOUT) × IOUT

An important note is that power dissipation can be minimized, and thus greater efficiency achieved, by proper selection of the system voltage rails. Proper selection allows the minimum input-to-output voltage differential to be obtained. The low dropout of the device allows for maximum efficiency across a wide range of output voltages.

The main heat conduction path for the device is through the thermal pad on the package. As such, the thermal pad must be soldered to a copper pad area under the device. This pad area contains an array of plated vias that conduct heat to any inner plane areas or to a bottom-side copper plane.

The maximum power dissipation determines the maximum allowable junction temperature (TJ) for the device. Power dissipation and junction temperature are most often related by the junction-to-ambient thermal resistance (RθJA) of the combined PCB, device package, and the temperature of the ambient air (TA), according to Equation 2. The equation is rearranged for output current in Equation 3.

Equation 2. TJ = TA + RθJA × PD
Equation 3. IOUT = (TJ – TA) / [RθJA × (VIN – VOUT)]

Unfortunately, this thermal resistance (RθJA) is highly dependent on the heat-spreading capability built into the particular PCB design, and therefore varies according to the total copper area, copper weight, and location of the planes. The RθJA recorded in the v table is determined by the JEDEC standard, PCB, and copper-spreading area, and is only used as a relative measure of package thermal performance. Note that for a well-designed thermal layout, RθJA is actually the sum of the package junction-to-case (bottom) thermal resistance (RθJCbot) plus the thermal resistance contribution by the PCB copper.

Figure 25 through Figure 30 show the functions of RθJA and ψJB vs. copper area and thickness. These plots are generated with a 101.6 mm x 101.6 mm x 1.6mm PCB of two and four layers. For the four layer board, inner planes use 1 oz copper thickness. Outer layers are simulated with both 1 oz and 2 oz copper thickness. A 2 x 1 array of thermal vias of 300 µm drill diameter and 25 µm Cu plating is located beneath the thermal pad of the device. The thermal vias connect the top layer, the bottom layer and, in the case of the 4-layer board, the first inner GND plane. Each of the layers has a copper plane of equal area.

TPS7B81-Q1 thetaja_vs_copper.gifFigure 25. RθJA versus Cu Area for the WSON (DRV) Package
TPS7B81-Q1 psijb_vs_copper.gifFigure 26. ψJB versus Cu Area for the WSON (DRV) Package
TPS7B81-Q1 thetaja_vs_copper_dgn.gifFigure 27. RθJA versus Cu Area for the HVSSOP (DGN) Package
TPS7B81-Q1 psijb_vs_copper_dgn.gifFigure 28. ψJB versus Cu Area for the HVSSOP (DGN) Package
TPS7B81-Q1 thetaja_vs_copper_kvu.gifFigure 29. RθJA versus Cu Area for the TO-252 (KVU) Package
TPS7B81-Q1 psijb_vs_copper_kvu.gifFigure 30. ψJB versus Cu Area for the TO-252 (KVU) Package