ZHCSGF3B July 2017 – January 2019 TPS7A92
PRODUCTION DATA.
The output voltage can be set to 1.2 V by selecting the correct values for R1 and R2; see Equation 3.
Input and output capacitors are selected in accordance with theCapacitor Recommendationsection. Ceramic capacitances of 22 µF for both input and output are selected to help balance the charge needed during startup when charging the output capacitor, thus reducing the input voltage drop.
To satisfy the required startup time (tSS) and still maintain low-noise performance, a 0.1-µF CNR/SS is selected for with SS_CTRL connected to VIN. This value is calculated with Equation 9. Using the INR/SS(MAX) and the smallest CNR/SS capacitance resulting from manufacturing variance (often ±20%) provides the fastest startup time, whereas using the INR/SS(MIN) and the largest CNR/SS capacitance resulting from manufacturing variance provides the slowest startup time.
With a 1.5-A maximum load, the internal power dissipation is 1.2 W, corresponding to a 91°C junction temperature rise. With a 55°C maximum ambient temperature, the junction temperature is at 124°C on the JEDEC standard high-K board. Connecting the thermal pad to more metal on the PCB than the standard JEDEC high-K board decreases the thermal resistance to the board and causes a decrease in the junction temperature of the device for a given power dissipation. To minimize noise, a feed-forward capacitance (CFF) of 10 nF is selected.
See the Layout section for an example of how to layout the TPS7A92 to achieve best PSRR and noise.