ZHCSHE9J June   2010  – January 2018 TPS7A80

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
    1.     Device Images
      1.      典型应用图
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Internal Current Limit
      2. 7.3.2 Shutdown
      3. 7.3.3 Start-Up
      4. 7.3.4 Undervoltage Lockout (UVLO)
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Dropout Voltage
        2. 8.2.1.2 Minimum Load
        3. 8.2.1.3 Input and Output Capacitor Requirements
        4. 8.2.1.4 Transient Response
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Output Noise
      3. 8.2.3 Application Curve
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Board Layout Recommendations to Improve PSRR and Noise Performance
      2. 10.1.2 Thermal Considerations
      3. 10.1.3 Power Dissipation
      4. 10.1.4 Estimating Junction Temperature
    2. 10.2 Layout Example
  11. 11器件和文档支持
    1. 11.1 文档支持
      1. 11.1.1 相关文档
    2. 11.2 接收文档更新通知
    3. 11.3 社区资源
    4. 11.4 商标
    5. 11.5 静电放电警告
    6. 11.6 Glossary
  12. 12机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

6.4 Thermal Information

THERMAL METRIC(1)(2) TPS7A80 UNIT
DRB (VSON)(3)
8 PINS
RθJA Junction-to-ambient thermal resistance 47.8 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 53.9 °C/W
RθJB Junction-to-board thermal resistance 23.4 °C/W
ψJT Junction-to-top characterization parameter 1 °C/W
ψJB Junction-to-board characterization parameter 23.5 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 7.4 °C/W
(1) For information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.
(2) For thermal estimates of this device based on PCB copper area, see the TI PCB Thermal Calculator.
(3) Thermal data for the DRB package are derived by thermal simulations based on JEDEC-standard methodology as specified in the JESD51 series. The following assumptions are used in the simulations:
  1. The exposed pad is connected to the PCB ground layer through a 2 × 2 thermal via array.
  2. The top and bottom copper layers are assumed to have a 5% thermal conductivity of copper representing a 20% copper coverage.
  3. This data were generated with only a single device at the center of a JEDEC high-K (2s2p) board with 3 inches × 3 inches copper area. To understand the effects of the copper area on thermal performance, refer to the Power Dissipation and Estimating Junction Temperature sections.