ZHCSK49E August   2019  – September 2022 TPS7A24

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1 Output Enable
      2. 7.3.2 Dropout Voltage
      3. 7.3.3 Current Limit
      4. 7.3.4 Undervoltage Lockout (UVLO)
      5. 7.3.5 Thermal Shutdown
      6. 7.3.6 Active Overshoot Pulldown Circuitry
    4. 7.4 Device Functional Modes
      1. 7.4.1 Device Functional Mode Comparison
      2. 7.4.2 Normal Operation
      3. 7.4.3 Dropout Operation
      4. 7.4.4 Disabled
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Adjustable Device Feedback Resistors
      2. 8.1.2 Recommended Capacitor Types
      3. 8.1.3 Input and Output Capacitor Requirements
      4. 8.1.4 Reverse Current
      5. 8.1.5 Feed-Forward Capacitor (CFF)
      6. 8.1.6 Power Dissipation (PD)
      7. 8.1.7 Estimating Junction Temperature
      8. 8.1.8 Special Consideration for Line Transients
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Transient Response
        2. 8.2.2.2 Selecting Feedback Divider Resistors
        3. 8.2.2.3 Thermal Dissipation
      3. 8.2.3 Application Curve
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Examples
  9. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Device Nomenclature
    2. 9.2 接收文档更新通知
    3. 9.3 支持资源
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 术语表
  10. 10Mechanical, Packaging, and Orderable Information

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订购信息

8.2.2.2 Selecting Feedback Divider Resistors

For this design example, VOUT is set to 5 V. The following equations set the output voltage:

Equation 8. VOUT = VFB × (1 + R1 / R2)
Equation 9. R1 + R2 ≤ VOUT / (IFB × 100)

For improved output accuracy, use Equation 9 and IFB(TYP) = 10 nA as listed in the Section 6.5 table to calculate the upper limit for series feedback resistance, R1 + R2 ≤ 5 MΩ.

The control-loop error amplifier drives the FB pin to the same voltage as the internal reference (VFB = 1.24 V as listed in the Section 6.5 table). Use Equation 8 to determine the ratio of R1 / R2 = 1.66. Use this ratio and solve Equation 9 for R2. Now calculate the upper limit for R2 ≤ 1.24 MΩ. Select a standard value resistor of R2 = 1.18 MΩ.

Reference Equation 8 and solve for R1:

Equation 10. R1 = (VOUT / VFB – 1) × R2

From Equation 10, R1 = 1.96 MΩ can be determined. From Equation 8, select VOUT = 3.299 V.