ZHCSN49M january   2007  – april 2023

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 描述
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics: Other Orderable Devices (non-M3 Suffix)
    6. 6.6  Electrical Characteristics: Orderable Device with M3 suffix
    7. 6.7  典型特性：IOUT = 50 mA
    8. 6.8  Typical Characteristics: IOUT = 1 A
    9. 6.9  Typical Characteristics: IOUT = 50 mA (M3 Suffix)
    10. 6.10 Typical Characteristics: IOUT = 1 A (M3 Suffix)
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Enable/Shutdown
      2. 7.3.2 Power Good
      3. 7.3.3 Internal Current Limit
      4. 7.3.4 Thermal Protection
    4. 7.4 Device Functional Modes
      1. 7.4.1 Normal Operation
      2. 7.4.2 Dropout Operation
      3. 7.4.3 Disabled
    5. 7.5 Programming
      1. 7.5.1 Programmable Soft-Start
      2. 7.5.2 Sequencing Requirements
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Adjusting the Output Voltage
      2. 8.1.2 Input, Output, and Bias Capacitor Requirements
      3. 8.1.3 Transient Response
      4. 8.1.4 Dropout Voltage
      5. 8.1.5 Output Noise
    2. 8.2 Typical Applications
      1. 8.2.1 FPGA I/O Supply at 1.5 V With a Bias Rail
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
      2. 8.2.2 FPGA I/O Supply at 1.5 V Without a Bias Rail
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
        3. 8.2.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
        1. 8.4.1.1 Estimating Junction Temperature
      2. 8.4.2 Layout Example
  9. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Development Support
        1. 9.1.1.1 Evaluation Modules
        2. 9.1.1.2 Spice Models
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 接收文档更新通知
    4. 9.4 支持资源
    5. 9.5 Trademarks
    6. 9.6 静电放电警告
    7. 9.7 术语表
  10. 10Mechanical, Packaging, and Orderable Information

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

6.7 典型特性：IOUT = 50 mA

条件为：TJ = 25°C、VIN = VOUT(nom) + 0.3V、VBIAS = 5V、IOUT = 50mA、VEN = VIN、CIN = 1μF、CBIAS = 4.7μF 且 COUT = 10μF（除非另有说明）

GUID-B39BB98F-5FE4-4A2C-8C65-80B9AEC1ADE4-low.gif
 
图 6-1 VIN 线性调整率
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图 6-3 负载调整率
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图 6-5 VIN 压降电压与 IOUT 和温度 (TJ) 间的关系
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图 6-7 VIN 压降电压与 (VBIAS – VOUT) 和温度 (TJ) 间的关系
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图 6-9 VBIAS PSRR 与频率间的关系
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图 6-11 VIN PSRR 与 (VIN – VOUT) 间的关系
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图 6-13 BIAS 引脚电流与输出电流和温度 (TJ) 间的关系
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图 6-15 软启动充电电流 (ISS) 与温度 (TJ) 间的关系
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图 6-17 电流限值与 (VBIAS – VOUT) 间的关系
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图 6-2 VBIAS 线性调整率
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图 6-4 轻负载下的负载调整率
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图 6-6 VIN 压降电压与 (VBIAS – VOUT) 和温度 (TJ) 间的关系
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图 6-8 VBIAS 压降电压与 IOUT 和温度 (TJ) 间的关系
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图 6-10 VIN PSRR 与频率间的关系
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图 6-12 噪声频谱密度
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图 6-14 BIAS 引脚电流与 VBIAS 和温度 (TJ) 间的关系
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图 6-16 低电平 PG 电压与电流间的关系