at VIN = VOUT(NOM) – 0.5V,
VOUT = -2.5V, = IOUT = 1mA, VEN = 1.5V,
COUT = 2.2μF, and CNR = 0.01μF (unless otherwise
noted)
Figure 5-1 Output Voltage vs Input Voltage (legacy chip)
Figure 5-3 Output Voltage vs Ambient Temperature (legacy chip)
Figure 5-5 TPS72301 Dropout Voltage vs Input Voltage (legacy chip)
Figure 5-7 Dropout Voltage vs Output Current (legacy chip)
Figure 5-9 Dropout Voltage vs Output Current (light loads, new
chip)
Figure 5-11 TPS72325 Dropout Voltage vs Junction Temperature
(new chip)
Figure 5-13 Ground Current vs Input Voltage (new chip)
Figure 5-15 Ground Current vs Output Current (new chip)
Figure 5-17 Ground Current vs Junction Temperature (new
chip)
Figure 5-19 TPS72325 Current Limit vs Junction Temperature (new
chip)
Figure 5-21 Standby Current vs Junction Temperature (legacy chip)
Figure 5-23 Standby Current vs VIN (new chip)
Figure 5-25 TPS72301 Feedback Pin Current vs Junction
Temperature (new chip)
Figure 5-27 Enable Pin Current vs Junction Temperature (new
chip)
Figure 5-29 Line Regulation vs Junction Temperature (new
chip)
Figure 5-31 EN
Thresholds (Positive) vs Junction Temperature (new chip)
Figure 5-33 UVLO
vs Junction Temperature (new chip)
Figure 5-35 TPS72325 Line Transient Response (legacy chip)
| VIN = -3V to -4V with
dVIN/dt = 1V/µs, IOUT =
200mA |
Figure 5-37 TPS72325 Line Transient Response (new chip)
| VIN = -3V to -10V with
dVIN/dt = 1V/µs, IOUT =
200mA |
Figure 5-39 TPS72325 Line Transient Response (new chip)
| VIN = -2.5V to -5.0V with
dVIN/dt = 2V/µs, IOUT =
1mA |
Figure 5-41 TPS72325 Dropout exit Response (new chip)
Figure 5-43 TPS72325 Load Transient Response (legacy chip)
| IOUT = 1µA to 200mA with
dIOUT/dt = 0.2A/µs |
Figure 5-45 TPS72325 Load Transient Response (new chip)
Figure 5-47 TPS72325 Start-Up Response (legacy chip)
Figure 5-49 TPS72325 Power-Up/Power-Down (legacy chip)
Figure 5-51 TPS72325 Start-up Response (VIN ramping
before EN) (New chip)
Figure 5-53 TPS72325 Start-up Response (VIN ramping
after EN) (New chip)
Figure 5-55 TPS72325 Start-up Response (VIN & EN
tied together) (New chip)
Figure 5-57 Start-up inrush current vs COUT (New
chip)
Figure 5-59 TPS72325 Total Noise vs CNR (10Hz to 10MHz) (New chip)
Figure 5-61 TPS72325 Total Noise vs IOUT (10Hz to 10MHz) (New chip)
Figure 5-63 TPS72325 Total Noise vs VIN (10Hz to 10MHz) (New chip)
Figure 5-65 TPS72325 Total Noise vs COUT (10Hz to 10MHz) (New chip)
Figure 5-67 TPS72325 Output Noise vs
Time (legacy chip)
Figure 5-69 TPS72325 Noise Spectral Density vs Frequency (legacy chip)
Figure 5-71 PSRR
vs Frequency (legacy chip)
Figure 5-73 PSRR vs CNR (New chip)
Figure 5-75 PSRR vs VIN (New chip)
Figure 5-77 PSRR vs COUT (New chip)
Figure 5-79 PSRR vs CFF (adjustable only) (New
chip)
Figure 5-2 Output Voltage vs Input Voltage (new chip)
Figure 5-4 Output Voltage vs Ambient Temperature (new
chip)
Figure 5-6 TPS72301 Dropout Voltage vs Input Voltage (new
chip)
Figure 5-8 Dropout Voltage vs Output Current (new chip)
Figure 5-10 TPS72325 Dropout Voltage vs Junction Temperature (legacy chip)
Figure 5-12 Ground Current vs Input Voltage (legacy chip)
Figure 5-14 Ground Current vs Output Current (legacy chip)
Figure 5-16 Ground Current vs Junction Temperature (legacy chip)
Figure 5-18 TPS72325 Current Limit vs Junction Temperature (legacy chip)
Figure 5-20 TPS72325 Current Limit vs VIN (new
chip)
Figure 5-22 Standby Current vs Junction Temperature (new chip)
Figure 5-24 TPS72301 Feedback Pin Current vs Junction Temperature (legacy chip)
Figure 5-26 Enable Pin Current vs Junction Temperature (legacy chip)
Figure 5-28 Line
And Load Regulation vs Junction Temperature (legacy chip)
Figure 5-30 Load Regulation vs Junction Temperature (new
chip)
Figure 5-32 EN
Thresholds (Negative) vs Junction Temperature (new chip)
Figure 5-34 TPS72301 Minimum Required Input Voltage vs Output Voltage (legacy
chip)
| VIN = -3V to -4V with
dVIN/dt = 1V/µs, IOUT =
1mA |
Figure 5-36 TPS72325 Line Transient Response (new chip)
| VIN = -3V to -10V with
dVIN/dt = 1V/µs, IOUT =
1mA |
Figure 5-38 TPS72325 Line Transient Response (new chip)
| VIN = -2.5V to -10V with
dVIN/dt = 2V/µs, IOUT =
1mA |
Figure 5-40 TPS72325 Dropout exit Response (new chip)
Figure 5-42 TPS72325 Load Transient Response (legacy chip)
| IOUT = 1µA to 200mA with
dIOUT/dt = 1A/µs |
Figure 5-44 TPS72325 Load Transient Response (new chip)
| IOUT = 1mA to 200mA with
dIOUT/dt = 0.2A/µs |
Figure 5-46 TPS72325 Load Transient Response (new chip)
Figure 5-48 TPS72325 Start-Up Response (legacy chip)
| IOUT = 0mA, CNR not
conneted. |
Figure 5-50 TPS72325 Start-up time vs Temp (new chip)
Figure 5-52 TPS72325 Start-up Response (VIN ramping
before EN) (New chip)
Figure 5-54 TPS72325 Start-up Response (VIN ramping
after EN) (New chip)
Figure 5-56 TPS72325 Start-up Response (VIN & EN tied together) (New
chip)
Figure 5-58 TPS72325 Total Noise vs CNR (10Hz to 100kHz) (legacy
chip)
Figure 5-60 TPS72325 Total Noise vs CNR (10Hz to 10MHz) (New chip)Figure 5-62 TPS72325 Total Noise vs VIN (10Hz to 10MHz) (New chip) 
Figure 5-64 TPS72325 Total Noise vs COUT (10Hz to 10MHz) (New chip)
Figure 5-66 TPS72301 Total Noise vs CFF (10Hz to 10MHz) (New chip)
Figure 5-68 TPS72325 Noise Spectral Density vs Frequency (legacy chip)
Figure 5-70 PSRR
vs Frequency (legacy chip)
Figure 5-72 PSRR vs CNR (New chip)
Figure 5-74 PSRR vs IOUT (New chip)
Figure 5-76 PSRR vs VIN (New chip)
Figure 5-78 PSRR vs COUT (New chip)