7.3.1 State Diagram

The state diagram below details the basic operation of this device.

Figure 6. State Diagram

7.3.2 Power-up Timing

The timing diagram below details the state of the input signals and output voltages in a power-up event.

Figure 7. Power-up Timing

7.3.3 GPO

The TPS657095 has one general purpose output (GP0) that can be used to control a camera image sensor. Bit 0 of the GPIO_CTRL Register can be used to set the output level and bit 1 of the GPIO_CTRL Register can be used to define whether the output is an open-drain or push-pull output. Internally, the GPO output buffer is connected to LDO1. Therefore, LDO1 has to be enabled in order for the GPO output to operate. In the open-drain configuration, the external pull-up resistor should be pulled up to a voltage that is equal to or less than VCC at all times. Connecting the pull-up resistor to a voltage source that is greater than VCC or present whenever VCC is not present may cause an unwanted leakage path.

7.3.4 GPIO

The TPS657095 has one general purpose input/output (GPIO) that can be used to control an external device when configured as an output. When configured as an input, the GPIO pin serves as a dedicated LDO2 enable. This discrete pin is 'ORed' with the software LDO2 enable. The functionality is shown in the following table.

The GPIO_CTRL register contains the bits used to configure this GPIO. Bit 3 of the GPIO_CTRL Register can be used to set the output level, bit 4 can be used to configure the GPIO as an input or an output, and bit 5 of the GPIO_CTRL Register can be used to define whether the output is an open-drain or push-pull output. Internally, the GPIO output buffer is connected to LDO1. Therefore, LDO1 has to be enabled in order for the GPIO to operate. In the open-drain configuration, the external pull-up resistor should be pulled up to a voltage that is equal to or less than VCC at all times. Connecting the pull-up resistor to a voltage source that is greater than VCC or present whenever VCC is not present may cause an unwanted leakage path.

7.3.5 LED_EN

The TPS657095 has a pin, LED_EN, which is used to control a privacy LED. The privacy LED can only be turned on or off using the LED_EN pin. No other means to control the privacy LED exists in this device. Operation of the LED_EN pin as it relates to minimum on time is shown in the Minimum-On-Time feature section of this document. The LED driver circuit of this device is internally biased by an internal 1.8V reference which is automatically powered once a valid voltage is present on the VCC/AVCC pins of this device. The input leakage current specifed in the Electrical Characteristics section of this datasheet will not be exeeded even if a logic high voltage is applied to this pin while VCC/AVCC are not present.

7.3.6 Minimum-On-Time Feature

In order to ensure proper operation of a privacy LED, the TPS657095 device incorporates a Minimum-On-Time feature. The Minimum-On-Time for this device is programmed at the factory to a specified value which is shown in the MIN_ON_TIME_THR Register. The user programmable Minimum-On-Time Register can be used to set a minimum on time for the LED. .

Once the Minimum-On-Time Register is loaded with a value and the internal PWM is enabled, the Minimum-On-Time timer will count to the value loaded. Writing a new value to the Minimum-On-Time Register prior to the timer expire will only take effect after the timer expires and the internal PWM is re-enabled.

Figure 8. Minimum-On-Time Timing Diagrams

7.3.7 PWM Dimming

LED_EN serves as the enable for the internal PWM.

• LED_EN = 0: LED is OFF
• LED_EN = 1: LED is ON / internal PWM is enabled

Since the crystal oscillator is needed for the internal PWM dimming, it is automatically enabled based on the status of the LED_EN pin and on the CLKout_EN register bit.

7.3.8 Crystal Oscillator and CLKOUT

The crystal oscilaltor is used to provide a clock signal to the camera image sensor via the CLKOUT pin. It is also used to control the internal PWM for dimming the LED and as the clock for the Minimum-On-Time counter. The crystal oscillator is enabled by either the CLKout_EN bit in the PWM_OSC_CNTRL register or by driving the LED_EN pin to a high state. Since the Minimum-On-Time counter is started when the LED_EN input is driven to a high state, the crystal oscillator will remain on if the LED_EN pin is driven to a low state and the Minimum-On-Time counter has yet to time out.

The CLKOUT buffer is internally supplied by LDO1, hence LDO1 needs to be enabled for proper functionality of the clock output. the CLKOUT buffer is enabled only when bit 2 of the PWM_OSC_CNTRL Register is set to a logic one. If bit 2 of the PWM_OSC_CNTRL register is set to a logic one while LDO1 is disabled, the crystal oscillator will run but the clock output will not be present on the CLKOUT pin. The OSC_FREQ[1:0] bits in the PWM_OSC_CNTRL Register should be set prior to enabling the CLKOUT buffer.

In addition, the crystal oscillator is driving the internal charge pump that generates the programming voltage for the 4kByte OTP memory. For programming the OTP, the oscillator has to be enabled by setting CLKout_EN to a logic '1' at least 10ms before the OTP is written to allow the crystal to stabilize.

The oscillator circuit used does not require external components other than the crystal itself on pins XI and XO. Internally, the oscillator circuit contains two 16pF capacitors connected from XI to GND and from XO to GND. It is designed for an equivalent series resistance of the crystal to be less than 100Ω. Therefore, a crystal must be used with a series resistance of less than this value and no other resistors in series or in parallel to the crystal must be added.

The signal on CLKOUT is delayed from the CLKout_EN bit enabling the output buffer until the oscillator is stable. Once it has stabilized, an additional internal wait time of 131072 clk cycles x 1/24MHz has been added internally to the design before the output is set active. Given the typical start-up time of the crystal oscillator, it is safe to assume the total start-up time which depends on the crystal used including the 131072 cycles of clk delay is less than 10ms.

7.3.9 LDOs

The low dropout voltage regulators are designed to operate with low value ceramic input and output capacitors. Both LDOs contain a current limit feature which is used at start up to control the voltage ramp time.

LDO1 is enabled by bit 0 of the LDO_CTRL register. LDO2 can be enabled by either bit 1 of the LDO_CTRL register or by the GPIO if configured as an input. Since the input buffer for the GPIO is powered by LDO1, LDO1 must be enabled before the GPIO pin can be used to enable LDO1. In the case of a thermal event, the register enable bits will be cleared with no auto-re-start feature so as to allow the application software to control the power sequencing of the LDOs.

7.3.10 Undervoltage Lockout

The undervoltage lockout circuit prevents the device from malfunctioning at low input voltages and from excessive discharge of the battery. It disables the complete device at low input voltages.

The supply voltage to the TPS657095 is internally sensed at pin AVCC. When the voltage at AVCC exceeds the UVLO limit, the internal enable signals turns HIGH and allows the device to operate. When the supply voltage drops below the UVLO limit, TPS657095 is forced OFF, all functions are disabled and the LDO output voltage discharge circuitry is forced ON to ramp down the output voltage. However, if the input voltage drops below 2V, the discharge circuit becomes inactive.

7.3.11 Power Up/Power Down Default States

The GPO, GPIO and CLKOUT pins contain internal buffers powered by LDO1. The following table shows their state during a power up (UVLO Rising) and power down (UVLO Falling) event.

Notes:

1. Output is 'off' as a result of no power supply. The output follows LDO1 to within a diode drop.

2. The GPIO_STATE bit (bit 3 in the GPIO_CTRL register) is forced to a logic low.

3. The default setting is configured as an input. This can be modified by using the GPIO_CTRL register.

7.3.12 Output Voltage Discharge for LDO1 and LDO2

The LDOs contain an output capacitor discharge feature which makes sure that the capacitor is discharged to GND when the supply voltage drops below the undervoltage lockout threshold. The discharge function is enabled when voltage is applied at AVCC starting at about 2.1V until the LDOs are enabled.

7.3.13 Power-Good Status Bits for LDO1 and LDO2

Bits PGOOD_LDO1 and PGOOD_LDO2 in register LDO_CTRL are driven by an comparator inside the LDOs to indicate when the output voltage is in regulation. The Bits are set 'high' when the LDO is in regulation. When the LDO is enabled but the voltage is not above the power-good threshold, the bit is set to a 'low' state. The bit is also set to a 'low' state if the LDO is disabled.

7.3.14 Short-Circuit Protection

All outputs are short circuit protected with a maximum output current as defined in the electrical specifications.

7.3.15 Thermal Shutdown

As soon as the junction temperature, T_J, exceeds 150°C (typically) for any of the LDOs, the LDO will go into thermal shutdown. In this case, the LDOs are turned-off. After the temperature has fallen below the threshold, the LDO remains off until it is enabled again by the I2C interface. There is no automatic power-on feature once the thermal event is past.

7.3.16 LED Driver

The TPS657095 contains a LED driver for a current of up to 30mA. ISINK is an open drain current sink that regulates a current in a LED. The anode of the LED needs to be tied to a positive supply voltage e.g., V_CC or any other voltage within the limits of the electrical spec of TPS657095, depending on the forward voltage of the LED. The cathode of the LED is connected to ISINK which sets a constant current to GND. ISINK is regulated internally based on the default current set internally. If the LED_EN pin is pulled LOW, the LED driver is disabled and its output ISINK is high resistive. If LED_EN is HIGH, the current sink regulates to the current defined by the setting in the ISINK_CURRENT Register.

The internal PWM generator allows for internal dimming with a frequency of 3kHz, 6kHz, 12kHz or 24kHz. A 10Bit duty cycle register allows to set the duty cycle in a range from 0% to 99.9% using 8Bits PWM resolution and another 2Bits of dithering.

A signal applied at the LED_EN pin is used to synchronously enable and disable the internal PWM signal.

7.3.17 4kByte OTP Memory

The TPS657095 contains 4kBytes of one-time-programmable (OTP) memory to store user data. The memory has a linear address range from 0x0000 to 0x0FFF and uses two Byte addressing as described in the serial interface description. Reading beyond the specified linear address range will result in reading all zeros. Writes to an address space beyond the specified linear address range are inhibited.

The 4kByte OTP memory requires a programming voltage higher than 5V. The program voltage is generated internally by a charge pump which uses the VCC voltage as its input. During programming, Vcc has to be kept at 5V +/-5% (a voltage of 5.25V is recommended) and the internal oscillator has to be enabled 10ms before programming to allow the 24MHz crystal to stabilize. The 24MHz clock is needed for the internal charge pump to generate the programming voltage from Vcc.

As an added security measure, programming the 4kByte OTP memory requires a two byte sequential password to be written to in the PMU register space at address 0x0F. The two bytes must be written back to back with no restriction on the delay between the writes. Any data written at address 0x0F that does not match the password and sequence will disable the ability to program the 4kByte OTP memory.

7.4.1 Shutdown Mode

The TPS657095 is in a 'Shutdown' mode if the voltage on the AVCC pin is below 1.8V. In this mode, the device will not respond to I2C commands nor will the LED_EN pin be operational.

7.4.2 Operational Mode

The TPS657095 enters an 'Operational' mode mode once a voltage greater than the UVLO limit is present on both the VCC and AVCC pins. In this mode, the I2C is active, the operation of the LED is controllable via the LED_EN pin and the LDOs can be enabled.

7.5.1 Serial Interface

The serial interface is compatible with the standard and fast mode I²C specifications, allowing transfers at up to 400kHz. The interface adds flexibility to the power supply solution, enabling most functions to be programmed to new values depending on the instantaneous application requirements and charger status to be monitored. Register contents remain intact as long as VCC remains above the UVLO threshold. The I²C interface is running from an internal oscillator that is automatically enabled when there is an access to the interface. Additional features supported by the I²C compatible interface are:

• multi-byte read/write capability
• clock stretching; specifically needed during OTP write

The 7bit device address for TPS657095 is:

• "100 1000" for the PMU user registers
• "101 1000" for the 4kByte OTP memory

For the PMU, at address "100 1000", the device address is followed by the 1Byte register address and 1Byte data (for a write instruction)

For the 4kByte OTP memory, at address "101 1000", the device address is followed by the 1Byte register address [7:0] followed by the second address Byte [15:8] and 1Byte data (for a write instruction) giving a 4kByte linear address range for the memory. Please note that the supply voltage range at pins VCC and AVCC during programming (writing) of the OTP memory is limited to 5V ±5%.

Attempting to read data from register addresses not listed in this section will result in 00h being read out.

For normal data transfer, DATA is allowed to change only when CLK is low. Changes when CLK is high are reserved for indicating the start and stop conditions. During data transfer, the data line must remain stable whenever the clock line is high. There is one clock pulse per bit of data. Each data transfer is initiated with a start condition and terminated with a stop condition. When addressed, the TPS657095 generates an acknowledge bit after the reception of each byte. The master device (microprocessor) must generate an extra clock pulse that is associated with the acknowledge bit. The TPS657095 must pull down the DATA line during the acknowledge clock pulse so that the DATA line is a stable low during the high period of the acknowledge clock pulse. The DATA line is a stable low during the high period of the acknowledge–related clock pulse. Setup and hold times must be taken into account. During read operations, a master must signal the end of data to the slave by not generating an acknowledge bit on the last byte that was clocked out of the slave. In this case, the slave device TPS657095 must leave the data line high to enable the master to generate the stop condition.

The interface is reset by the internal UVLO signal of TPS657095 or by a STOP condition. If the SCL and SDA signal is not stable at the time the UVLO threshold on pin Vcc is exceeded, the first communication may not be acknowledged and will have to be re-transmitted after a STOP condition.

Upon the application of power on the VCC/AVCC pins, the internal I2C buffers may sequence up in a manner that produces a false START. If a false START is detected, an internal synchronization clock will be enabled until a STOP condition is received. During the time that the internal synchronization clock is active, the device will consume an additional 120uA of current.

Figure 9. START and STOP Conditions

Figure 10. Serial Interface WRITE to TPS657095 User Registers

Figure 11. Serial Interface READ from TPS657095 User Registers

Figure 12. Serial Interface WRITE to TPS657095 OTP Memory

Figure 13. Serial Interface READ from TPS657095 OTP Memory

Figure 14. Bit Transfer on the Serial Interface

Figure 15. Acknowledge on the I²C Bus

Figure 16. Bus Protocol

7.6.1 DEV_AND_REV_ID Register Address: 00h

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7.6.2 OTP_REV Register Address: 01h

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7.6.3 GPIO_CTRL Register Address: 02h

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7.6.4 PWM_OSC_CNTRL Register Address: 03h

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7.6.5 ISINK_CURRENT Register Address: 04h

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7.6.6 LDO_CTRL Register Address: 05h

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7.6.7 LDO1_VCTRL Register Address: 06h

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7.6.8 LDO2_VCTRL Register Address: 07h

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7.6.9 PWM_DUTY_THR_L Register Address: 08h

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7.6.10 PWM_DUTY_THR_H Register Address: 09h

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7.6.11 MIN_ON_TIME_THR Register Address: 0Ah

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7.6.12 PWM_DUTY_L Register Address: 0Bh

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7.6.13 PWM_DUTY_H Register Address: 0Ch

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7.6.14 MIN_ON_TIME Register Address: 0Dh

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7.6.15 SPARE Register Address: 0Eh

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7.6.16 4K_OTP_PASSWORD Register Address: 0Fh

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