SLVSCA6C October   2013  – October 2017 TPS65311-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Switching Characteristics
    8. 7.8 Typical Characteristics
      1. 7.8.1 BUCK 1 Characteristics
      2. 7.8.2 BUCK 2 and BUCK3 Characteristics
      3. 7.8.3 BOOST Characteristics
      4. 7.8.4 LDO Noise Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Buck Controller (BUCK1)
      2. 8.3.2  Synchronous Buck Converters BUCK2 and BUCK3
      3. 8.3.3  BOOST Converter
      4. 8.3.4  Frequency-Hopping Spread Spectrum
      5. 8.3.5  Linear Regulator LDO
      6. 8.3.6  Gate Driver Supply
      7. 8.3.7  RESET
      8. 8.3.8  Soft Start
      9. 8.3.9  Power-on Reset Flag
      10. 8.3.10 WAKE Pin
      11. 8.3.11 IRQ Pin
      12. 8.3.12 VBAT Undervoltage Warning
      13. 8.3.13 VIN Over or Undervoltage Protection
      14. 8.3.14 External Protection
      15. 8.3.15 Overtemperature Detection and Shutdown
      16. 8.3.16 Independent Voltage Monitoring
      17. 8.3.17 GND Loss Detection
      18. 8.3.18 Reference Voltage
      19. 8.3.19 Shutdown Comparator
      20. 8.3.20 LED and High-Side Switch Control
      21. 8.3.21 Window Watchdog
      22. 8.3.22 Timeout in Start-Up Modes
    4. 8.4 Device Functional Modes
      1. 8.4.1 Operating Modes
        1. 8.4.1.1  INIT
        2. 8.4.1.2  TESTSTART
        3. 8.4.1.3  TESTSTOP
        4. 8.4.1.4  VTCHECK
        5. 8.4.1.5  RAMP
          1. 8.4.1.5.1 Power-Up Sequencing
          2. 8.4.1.5.2 Power-Down Sequencing
        6. 8.4.1.6  ACTIVE
        7. 8.4.1.7  ERROR
        8. 8.4.1.8  LOCKED
        9. 8.4.1.9  LPM0
        10. 8.4.1.10 SHUTDOWN
    5. 8.5 Programming
      1. 8.5.1 SPI
        1. 8.5.1.1 FSI Bit
    6. 8.6 Register Map
      1. 8.6.1 Register Description
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Buck Controller (BUCK1)
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Adjusting the Output Voltage for the BUCK1 Controller
          2. 9.2.1.2.2 Output Inductor, Sense Resistor, and Capacitor Selection for the BUCK1 Controller
          3. 9.2.1.2.3 Compensation of the Buck Controller
          4. 9.2.1.2.4 Bootstrap Capacitor for the BUCK1 Controller
        3. 9.2.1.3 BUCK 1 Application Curve
      2. 9.2.2 Synchronous Buck Converters BUCK2 and BUCK3
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
          1. 9.2.2.2.1 Adjusting the Output Voltage for the BUCK2 and BUCK3 Converter
          2. 9.2.2.2.2 Output Inductor Selection for the BUCK2 and BUCK3 Converter
          3. 9.2.2.2.3 Compensation of the BUCK2 and BUCK3 Converters
          4. 9.2.2.2.4 Bootstrap Capacitor for the BUCK2/3 Converters
        3. 9.2.2.3 BUCK2 and BUCK3 Application Curves
      3. 9.2.3 BOOST Converter
        1. 9.2.3.1 Design Requirements
        2. 9.2.3.2 Detailed Design Procedure
          1. 9.2.3.2.1 Adjusting the Output Voltage for the Boost Converter
          2. 9.2.3.2.2 Output Inductor and Capacitor Selection for the BOOST Converter
          3. 9.2.3.2.3 Compensation of the BOOST Converter
          4. 9.2.3.2.4 Output Diode for the BOOST Converter
        3. 9.2.3.3 BOOST Converter Application Curves
      4. 9.2.4 Linear Regulator
        1. 9.2.4.1 Design Requirements
        2. 9.2.4.2 Detailed Design Procedure
          1. 9.2.4.2.1 Adjusting the Output Voltage for the Linear Regulator
          2. 9.2.4.2.2 Output Capacitance for the Linear Regulator
        3. 9.2.4.3 Linear Regulator Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Buck Controller
      2. 11.1.2 Buck Converter
      3. 11.1.3 Boost Converter
      4. 11.1.4 Linear Regulator
      5. 11.1.5 Other Considerations
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

封装选项

机械数据 (封装 | 引脚)
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订购信息

11 Layout

11.1 Layout Guidelines

11.1.1 Buck Controller

  • Connect a local decoupling capacitor between the drain of Q3 and the source of Q2. The length of this trace loop should be short.
  • The Kelvin-current sensing for the shunt resistor should have traces with minimum spacing, routed in parallel with each other. Place any filtering capacitor for noise near the S1-S2 pins.
  • The resistor divider for sensing the output voltage connects between the positive pin of the output capacitor and the GND pin (IC signal ground). Do not locate these components and their traces near any switching nodes or high-current traces. The resistor divider for monitoring the output voltage is to be placed as close as possible to the sensing resistor divider, and should be connected to same traces.
  • Connect the boot-strap capacitance between the PH1 and BOOT1 pins, and keep the length of these trace loops as short as possible.
  • Connect the compensation network between the COMP1 pin and GND pin (IC signal ground).
  • Connect a local decoupling capacitor between the VREG and PGDN1 pin, and between the EXTSUP and PGND1 pin. The length of this trace loop should be short.

11.1.2 Buck Converter

  • Connect a local decoupling capacitor between VSUP2 and PGND2 respectively VSUP3 and PGND3 pins. The length of this trace loop should be short.
  • The resistor divider for sensing the output voltage connects between the positive pin of the output capacitor and the GND pin (IC signal ground). Do not locate these components and their traces near any switching nodes or high-current traces. The resistor divider for monitoring the output voltage is to be placed as close as possible to the sensing resistor divider, and should be connected to same traces.
  • Connect the boot-strap capacitance between the PH2 and BOOT2 respectively PH3 and BOOT3 pins, and keep the length of this trace loop as short as possible.
  • If COMP2 and/or COMP3 are chosen to be connected to ground, use the signal ground trace connected to GND pin for this.

11.1.3 Boost Converter

  • The path formed from the input capacitor to the inductor and the PH5 pin should have short trace length. The same applies for the trace from the inductor to Schottky diode D2 to the output capacitor and the VBOOST pin. Connect the negative pin of the input capacitor and the PGND5 pin together with short trace lengths.
  • The resistor divider for sensing the output voltage connects between the positive pin of the output capacitor and the GND pin (IC signal ground). Do not locate these components and their traces near any switching nodes or high-current traces.
  • Connect the compensation network between the COMP5 pin and GND pin (IC signal ground).

11.1.4 Linear Regulator

  • Connect a local decoupling capacitor between VSUP4 and GND (IC signal ground) pins. The length of this trace loop should be short.
  • The resistor divider for sensing the output voltage connects between the positive pin of the output capacitor and the GND pin (IC signal ground). Do not locate these components and their traces near any switching nodes or high-current traces.

11.1.5 Other Considerations

  • Short PGNDx and GND to the thermal pad.
  • Use a star ground configuration if connecting to a non-ground plane system. Use tie-ins for the compensation-network ground, voltage-sense feedback ground, and local biasing bypass capacitor ground networks to this star ground.

11.2 Layout Example

TPS65311-Q1 layout_slvsca6.gif Figure 41. TPS65311-Q1 Layout Example